1. 1D and 2D Bitstream Relocation for Partially Dynamically Reconfigurable Architecture BY Marco Novati [email_address] 3-Day DRESD: July 29, 2008

6. Xilinx FPGAs and Configuration Memory

7. Frame Addressing: Virtex, Virtex-E * Inspired to Virtex Series Configuration Architecture User Guide

8. Frame Addressing: Virtex2pro * Taken from Virtex-II Pro and Virtex-II Pro X FPGA User Guide

10. Frame Addressing: Virtex 4-5 (2/2) * Inspired to Virtex 4 & 5 Configuration Architecture User Guide

13. Relocation: The Problem

14. Relocation: Scenario

15. Relocation: Motivation

24. Target Architecture: YaRA

25. PPC Based YaRA STATIC AREA

27. Configuration Bitstream

28. BiRF & BiRF Square Block Diagram

29. The Parser

32. Synthesis Results: Area FPGA BiRF BiRF Square Family Model Generic Version Optimized Version Generic Version Optimized Version Virtex II Pro vp7 11.6 % 3.6 % − − Virtex II Pro vp20 5.8 % 1.8 % − − Virtex II Pro vp30 4.2 % 1.3 % − − Virtex 4 vlx40 − − 2.2 % 0.9 % Virtex 4 vlx60 − − 1.5 % 0.6 % Virtex 4 vlx100 − − 0.8 % 0.3 % Virtex 5 vlx50 − − 1.1 % 0.8 % Virtex 5 vlx85 − − 0.6 % 0.4 % Virtex 5 vlx110 − − 0.5 % 0.3 %

36. Relocation Time Results (1/4)

38. Relocation Time Results (3/4)

39. Relocation Time Results (4/4)

44. Questions