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M etodologie   di  P rogettazine  H ardware e  S oftware   Reconfigurable Computing - Design Flow  -
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Presentation status ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Compiler background ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Retargetable Compilers
Retargetable Compilers – Main Goals ,[object Object],[object Object],[object Object],Def .:  A   compiler is called  retargetable , if it  can be modified to generate assembly code for  different architectures, while reusing the largest  part of the compiler source code.
Retargetable Compilers - degrees ,[object Object],[object Object],[object Object],[object Object]
Presentation status ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Delft Workbench Objectives ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Delft Workbench Programming Paradigm ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Delft Workbench Workflow Re- targeted Compiler Binary Code SimpleScalar Performance Statistics FPGA int fact(int n) { if(n<1) return n else return(n*fact(n-1)); } Human Directives call  f(.)  HDL Architecture REVISE C2C NO Part I  Part II Part III … … Code f(.) HDL
[object Object],Delft Workbench The retargetable compiler
MOLEN Architecture ,[object Object]
Presentation status ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
LimboWARE: The idea ,[object Object],[object Object]
LimboWARE: When - Where ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
LimboWARE Execution path dependent choice ,[object Object],[object Object],[object Object]
Presentation status ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
VIRGIL: The objectives ,[object Object],[object Object],[object Object],[object Object],[object Object]
VIRGIL: Main steps ,[object Object],[object Object],[object Object],[object Object]
VIRGIL: Workflow HLR
VIRGIL: The Compiler
VIRGIL: The architecture YaRA - FPGA Layers
VIRGIL: Needs ,[object Object],[object Object],[object Object],[object Object],[object Object]
Questions

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