2. 2
Rationale and Innovation
Problem statement
Given a reconfigurable architecture, find an on-chip
position for each functional unit
Innovative contribution: taking into account
Target Device Heterogeneity
Target Device reconfiguation capabilities
Inter-FU Communication
3. 3
Aims
Considering the area assignment problem tailored for
reconfigurable architectures, provide
a formalization of the problem, and
an approach (in 3 algorithms) for solving
6. Reconfigurable Architectures - I
On FPGAs
Reconfigurable Devices
Heterogeneous
Reconfiguration Limits
Different types of
Reconfigurable Architectures:
Total
Partial (Static)
Partial (Dynamic)
6
10. Area Assignment Problem
Let consider a Reconfigurable Architecture
Given a scheduled task graph (TG) of the application
Node: Reconfigurable Functional Unit (RFU) [*],
A netlist obtained after post synthesis and technology
mapping (i.e., before placement and routing)
Aim: find an area assignment for each RFU
10
[*] K. Bazargan, R. Kastner, M.S.: 3-d floorplanning: Simulated annealing and greedy placement methods for
reconfigurable computing systems. IEEE Rapid Systems Prototyping (1999)
11. Related Works - I
[*] introduced the concept of 3D floorplanning for
reconfigurable systems
SA in order to solve HW/SW codesign problem
For each task choose between
HW implementation
SW implementation
Limits
No device limits
considered
No communication
infrastructure
11
[*] K. Bazargan, R. Kastner, M.S.: 3-d floorplanning: Simulated annealing and greedy placement methods for
reconfigurable computing systems. IEEE Rapid Systems Prototyping (1999)
12. Related Works - II
[*] is the state of art in 3D floorplanning
Simulated Annealing over Transitive Closure Graph
Takes into account device reconfiguration limits
Limits
No heterogeneity considered
High overhead communication
infrastructure solution [**]
12
[*] Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen: Temporal Floorplanning Using 3D-subTCG,
Design Automation Conference, 2004
[**] S. P. Fekete, E. Kohler, and J. Teich: Optimal FPGA Module Placement with Temporal Precedence
Constraints, Proc. DATE, 2001.
14. Floorplanning vs. Placement
Characteristic Floorplanning Placement
# items <100 >10.000
Items (for FPGAs) IP-Core Slice, CLB
Aim Find a position for each item
obj. function depends mainly on Area mainly on Wirelength
Constraints Items can be positioned
everywhere
There is a set of
possible positions
14
Placement
Floor plan
15. Floorplacement - I
Hierarchical Approach (Floorplanning + Partitioning)
15
S. N. Adya, I. L. Markov, Fixed-outline Floorplanning: Enabling Hierarchical Design, IEEE Transaction on VLSI
System, 2002
S. N. Adya, S. Chaturvedi, J. A. Roy, David A. Papa, I. L. Markov: Unification of Partitioning, Placement and
Floorplanning , IEEE Intl. Conf. on CAD, 2004
16. Floorplacement - II
Reconfigurable Functional Unit (RFU)
A netlist obtained after post synthesis and technology
mapping (i.e., before placement and routing)
Reconfigurable Region (RR)
16
17. Floorplacement - III
Resource Aware (i.e., not all positions are feasible)
Device heterogeneity
Device Reconfiguration
capabilities
17
19. Proposed Problem Definition
19
Aim
Define RRs
For each task find
find a RR
A position inside RR
Objective Function
Min. Fragmentation
Constraints
Communication issues
Device limits
20. Target Devices: Xilinx Virtex 4 - 5
Target architecture based on EAPR design flow
Target Architecture and Devices
20
23. 1st Algorithm: Partitioning into RR
Aim: identify the RRs and associate each RFU to one RR
How: partitioning the TG minimizing resource
requirement variance of the RRs (moving and swapping
nodes)
23
Resource of type t
required by RFU n,
at static photo p
24. 2nd Algorithm:TFiRR - I
24
Temporal Floorplacement inside RR (TFiRR)
Aim: for each RR find a set of feasible width-height pairs
How: floorplacing RFUs inside corresponding RR
Assumption: RFUs’ height = height of the RR they belong to
Pseudo Code:
31. 3rd Algorithm: RR floorplacement - I
Simulated Annealing
Objective Function
Data Structure
4 Constraint Lists (one per row)
31
32. 3rd Algorithm: RR floorplacement - II
Simulated Annealing: moves
Swap two RRs
Move one RRs
Span over one more row
Un-Span over one less row
After each move packing is performed
(i.e., the floorplacement is compressed)
32
39. Partitioning’s impact on TFiRR
TFiRR on
Partitioned TG
TFiRR on TG
Execution Time 125ms 114ms 4m54s
Width
(normalized)
1.00 1.19 1.04
39
Increasing the number of RFUs decreases the possibility
to pick up the right one
Partitioning is a precondition of the 3rd algorithm in order
to better exploit FPGA’s area (2D Floorplacement)
40. Tests performed directly floorplacing RFUs
Execution time about 100 ms (100K iterations)
Floorplacement – Success Rate
40
43. State of the art
43
Authors Comm.
Infrastructure
Resource
Aware
Reconfiguration
Aware
Device Limits
Aware
Bazargan et al. No No Yes No
Yuh et al. Limited, w/
High Overhead
No Yes Yes
Singhal et al. No No Yes No
Feng et al. No Yes No No
44. Notes
The comparsion is performed with respect to the
description given by Yuh et al in [*]
Yuh’s approach does not support
Multiple Resources
Existence of a Static side
In order perform the comparison
the case study has been chosen in order to avoid
multiple resource limitation
Yuh’s approach has been extended to support a static
side
44
[*] Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang, Hsin-Lung Chen: Temporal Floorplanning Using 3D-subTCG,
Design Automation Conference, 2004
45. The Case Study
A Reconfigurable Architecture (for Biomedical Purpose)
on XC5VLX30T
1. Collecting data from sensor
2. Elaborating them
3. Sending to a host computer thorough the net
45
49. Conclusions - I
An algorithm for the identification of area constraint
for reconfigurable architectures has been introduced
Novelties: taking into account
Target device heterogeneity
Target device reconfiguration capabilities
Communication issues
49
50. Conclusions - II
Results have been published
A. Montone, M.D. Santambrogio, D. Sciuto,
A Design Workflow for the Identification of Area
Constraints in Dynamic Reconfigurable Systems,
IEEE International Symposium on Electronic Design, Test
and Applications (DELTA), 2008
A. Montone, M.D. Santambrogio,
Area Constraint Evaluation for FPGAs,
The Syndicated Q1-2008, A technical newsletter for
FPGA, ASIC Verification and DSP Designers,
Synplicity Incorporation
Under revision:
A Reconfiguration-aware Floorplacer for FPGAs,
IEEE Field Programmable Logic (FPL), 2008
50
51. Future Works
Take into consideration IOBs and inter modules
communications
Partitioning considering clock regions
51
