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Modeling Methodologies for Dynamic Reconfigurable Systems Thesis

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Marco Santambrogio
Marco Santambrogio
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Modeling Methodologies for Dynamic Reconfigurable Systems Thesis Defense - May 2008 Fabio Cancare Thesis Committee: Tanya Berger-Wolf, Shantanu Dutt (Chair), Donatella Sciuto
Rationale ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Understand how it is possible to exploit the model-design paradigm in dynamic reconfigurable system implementation
Innovative Contribution ,[object Object]
Useful Novelties ,[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Reconfigurable Computing “ Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much higher performance than software, while maintaining a higher level of flexibility than hardware” (K. Compton and S. Hauck, Reconfigurable Computing: a Survey of Systems and Software , 2002)‏
Reasons Behind ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Reconfigurable Computing Techniques ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Useful Definitions ,[object Object],[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Flow Overview ,[object Object],[object Object],[object Object],[object Object],[object Object]
High Level Modeling Phase ,[object Object]
HLMP – Tools and Techniques ,[object Object],[object Object],[object Object]
Simulink HDL Coder Compliant Models
HLMP – Reconfiguration Aware Modeling
HLMP – Reconfiguration Unaware Modeling ,[object Object]
Low Level Implementation Phase
System Generation
LLIP – The Caronte Flow and SysGen ,[object Object],SysGen
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Real-world Application ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Overall Description
Real-world Application – System Model
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Classical System ,[object Object],FPGA Logical view FPGA Physical view Base Arch. RGB to grayscale Edge detection Circle detection Slot detection
Dynamic Reconfigurable System ,[object Object],FPGA Logical view Physical view Static Area Base Arch. Rec. Area RFU Free Resource
Occupation Data Static System Dynamic Reconfigurable System
Classic System vs DR System
Scientific Papers ,[object Object],[object Object],[object Object],[object Object]
Outline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Conclusions and Follow-ups ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
General Information ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Any Question? ,[object Object]

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