https://www.udemy.com/vlsi-academy The very first step in chip design is floorplanning, in which the width and height of the chip, basically the area of the chip, is defined. A chip consists of two parts, 'core' and 'die'.

1. Memory Processor
output
Input
Power
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2. Intro slide {Speed, Functionality (touch screen,
Internet, chatting, etc), Battery
Power, Size, etc …… “
………….
………….
Specifications
To
RTL module 8085 (clk, rst1, rst2, en, ….
)
….
….
…..
End module
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3. {Speed, Functionality (touch screen,
Internet, chatting, etc), Battery
Power, Size, etc …… “
………….
………….
Specifications
To
RTL module 8085 (clk, rst1, rst2, en, ….
)
….
….
…..
End module
RTL
To
GDS
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4. {Speed, Functionality (touch screen,
Internet, chatting, etc), Battery
Power, Size, etc …… “
………….
………….
Specifications
To
RTL module 8085 (clk, rst1, rst2, en, ….
)
….
….
…..
End module
RTL
To
GDS
GDS
To
Fabrication
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5. {Speed, Functionality (touch screen,
Internet, chatting, etc), Battery
Power, Size, etc …… “
………….
………….
Specifications
To
RTL module 8085 (clk, rst1, rst2, en, ….
)
….
….
…..
End module
RTL
To
GDS
GDS
To
Fabrication
We will explore the Physical Aspects of Chip Design
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6. We will explore the Physical Aspects of Chip Design
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7. We will explore the Physical Aspects of Chip Design
The first step to understand the physical aspects of a chip is
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8. We will explore the Physical Aspects of Chip Design
The first step to understand the physical aspects of a chip is
Area of Core and Die of Chip
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9. We will explore the Physical Aspects of Chip Design
The first step to understand the physical aspects of a chip is
Area of Core and Die of Chip
Die
Core
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10. Let’s Begin with a netlist
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11. Let’s Begin with a netlist
a
A1 y
D Q b D Q
a
FF O1 y FF
b
Clk
FF = FlipFlops/Latches/Registers
A1, O1 = Standard Cells (AND, OR, INVERTER)
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12. Let’s Begin with a netlist
a
A1 y
D Q b D Q
a
FF O1 y FF
b
Clk
FF = FlipFlops/Latches/Registers
A1, O1 = Standard Cells (AND, OR, INVERTER)
Consider, a netlist with 2 flops and 2 gates, with above shown connections
Note : A "netlist" describes the connectivity of an electronic design.
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13. a
A1 y
D Q b D Q
a
FF O1 y FF
b
Clk
FF = FlipFlops/Latches/Registers
A1, O1 = Standard Cells (AND, OR, INVERTER)
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14. Now, lets convert the highlighted symbols into physical dimension
a
A1 y
D Q b D Q
a
FF O1 y FF
b
Clk
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15. Now, lets convert the highlighted symbols into physical dimension
a
A1 y
D Q b D Q
a
FF O1 y FF
b
Clk
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
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16. Now, lets convert the highlighted symbols into physical dimension
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
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17. Let’s group combinational gates together into standard cells
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
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18. Let’s group combinational gates together into standard cells
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
a Std.
y
b Cells
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19. Let the length and breadth of std cell be 1 unit
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
a Std.
y
b Cells
1 unit
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20. Let the length and breadth of std cell be 1 unit
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
a Std. 1 unit
y
b Cells
1 unit
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21. Thus, the area of 1 std cell = 1 sq.unit
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
Area
a Std. 1 unit
y
b Cells
1 unit
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22. Thus, the area of 1 std cell = 1 sq.unit
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
Area
a Std. 1 unit 1 sq. unit
y
b Cells
1 unit
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23. Similarly, let’s group flops together, assign dimensions, and calculate area
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
Area
a Std. 1 unit 1 sq. unit
y
b Cells
1 unit
D Q
FF
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24. Similarly, let’s group flops together, assign dimensions, and calculate area
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
Area
a Std. 1 unit 1 sq. unit
y
b Cells
1 unit
Area
D Q
1 unit 1 sq. unit
FF
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25. Let us understand
The area occupied by the below netlist on a Silicon Wafer
a
A1 y
D Q b D Q
a a
FF O1 yy FF
b b
Clk
Area
a Std. 1 unit 1 sq. unit
y
b Cells
1 unit
Area
D Q
1 unit 1 sq. unit
FF
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26. D Q
FF
a
A1 y
b D Q
a a
O1 yy FF
b b
Area
a Std. 1 unit 1 sq. unit
y
b Cells
1 unit
Area
D Q
1 unit 1 sq. unit
FF
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27. D Q D Q
FF FF
a
A1 y
b
a a
O1 yy
b b
Area
a Std. 1 unit 1 sq. unit
y
b Cells
1 unit
Area
D Q
1 unit 1 sq. unit
FF
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28. D Q D Q
FF FF
a
A1 y
b a a
O1 yy
b b
Area
a Std. 1 unit 1 sq. unit
y
b Cells
1 unit
Area
D Q
1 unit 1 sq. unit
FF
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29. D Q D Q
FF FF
a a a
A1 y O1 yy
b b b
Let’s group flops and std cells together, assign dimensions, and calculate area
Area
a Std. 1 unit 1 sq. unit
y
b Cells
1 unit
Area
D Q
1 unit 1 sq. unit
FF
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30. D Q D Q
FF FF 1 unit
Area
4 sq. unit
a a a
A1 y O1 yy 1 unit
b b b
1 unit 1 unit
Let’s group flops and std cells together, assign dimensions, and calculate area
Area
a Std. 1 unit 1 sq. unit
y
b Cells
1 unit
Area
D Q
1 unit 1 sq. unit
FF
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31. D Q D Q
FF FF Now, lets understand,
What is ‘core’ and ‘die’ Section of a chip ?
and
a a a How to arrive on its dimensions?
A1 y O1 yy
b b b
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32. D Q D Q
FF FF
What is ‘core’ and ‘die’ Section of a chip ?
a a a
A1 y O1 yy
b b b
Core
A 'core' is the section of the chip where
the fundamental logic of the design is
placed.
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33. D Q D Q
FF FF
What is ‘core’ and ‘die’ Section of a chip ?
a a a
A1 y O1 yy
b b b
Die
Core
A ‘die’, which consists of core, is small
semiconductor material specimen on
which the fundamental circuit is
fabricated.
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34. How to arrive on its dimensions?
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
Place all logical cells inside the ‘core’
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35. As shown below, the logical cells occupies
the complete area of the core, the core is
said to be 100% utilized.
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
100 % Utilization
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36. (Area Occupied by Netlist)
Utilization Factor = -------------------------------------
(Total Area of the Core)
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
100 % Utilization
Therefore in above case,
Utilization factor = 4 sq. unit/4 sq. unit = 1
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Aspect Ratio = Height / Width = 2 unit / 2 unit = 1

37. Now, let us understand
The impact on “Utilization factor” and
“Aspect Ratio”, by varying ‘core width’
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
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38. As shown below, the logical cells occupies
‘half’ the area of the core, the core is said
to be 50% utilized.
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
50 % Utilization
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39. (Area Occupied by Netlist)
Utilization Factor = -------------------------------------
(Total Area of the Core)
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
50 % Utilization
Therefore in above case,
Utilization factor = 4 sq. unit/8 sq. unit = 0.5
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Aspect Ratio = Height / Width = 2 unit / 4 unit = 0.5

40. Now, let us understand
The impact on “Utilization factor” and
“Aspect Ratio”, by varying ‘core width’
and ‘core height’
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
Core and dei relation
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41. As shown below, the logical cells
occupies ‘one-fourth’ the area of the
core, the core is said to be 25%
utilized.
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
25 % Utilization
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42. (Area Occupied by Netlist)
Utilization Factor = -------------------------------------
(Total Area of the Core)
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
25 % Utilization
Therefore in above case,
Utilization factor = 4 sq. unit/16 sq. unit = 0.25
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Aspect Ratio = Height / Width = 4 unit / 4 unit = 1

43. D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
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44. Therefore, what is utilization factor?
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
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45. Therefore, what is utilization factor?
(Area Occupied by
Netlist)
Utilization Factor =
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
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46. Therefore, what is utilization factor?
(Area Occupied by
Netlist)
Utilization Factor = -------------------------
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
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47. Therefore, what is utilization factor?
(Area Occupied by
Netlist)
Utilization Factor = -------------------------
(Total Area of the
Core)
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
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48. Therefore, what is utilization factor?
(Area Occupied by
Netlist)
Utilization Factor = -------------------------
(Total Area of the
Core)
D Q D Q
FF FF
Die
a a a
A1 y O1 yy
b b b
Core
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49. With above netlist area (4 sq. unit), and, varying Width and height of the core,
we will observe the variations happening in UF (utilization factor) and AR (aspect ratio)
Sr. No. Width Height Area of Core UF AR
1) 5 3.2 16 0.25 0.64
2) 3.2 5 16 0.25 1.5625
3) 2 8 16 0.25 4
4) 4 4 16 0.25 1
5) 8 2 16 0.25 0.25
In the above table, in spite of varying width and height of the core,
UF and Area of core remains the same, but Aspect Ratio varies.
Thus, it is observed, AR decides the shape of the chip.
In above table, option 4) will give a square chip, and others will form a rectangular chip.
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50. UF Netlist AR
• Chip specification
will define UF, AR Area of
and Netlist. Core
• UF and netlist will
decide the ‘Area’ of
the core.
• ‘Area’ of the core
and AR will decide
the Shape, Width H
and Height of the
core.
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W

51. Thus we can define Width and Height of Core and Die.
H
Die
Core
W
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