AMD will be revealing details of two new core architectures - Bulldozer and Bobcat - at Hot Chips 22

1. “Bulldozer” and “Bobcat” AMD’s Latest x86 Core Innovations HotChips22

2. Two x86 Cores Tuned for Target Markets Mainstream Client and Server Markets “Bulldozer” Performance & Scalability Low PowerMarkets Small Die Area Cloud Clients Optimized “Bobcat” Flexible, Low Power & Small

3. The Bulldozer Architecture “Bulldozer” An innovative design that delivers true core functionality by pairing two integer execution cores with components that can be shared as needed Instruction Set extensions to increase capability of the design Extensive new power efficiency innovations Manufactured on the latest 32nm SOI technology Fetch Decode IntegerScheduler IntegerScheduler FP Scheduler Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline 128-bitFMAC 128-bitFMAC L1 DCache L1 DCache Shared L2 Cache

5. Threads compete for resources

7. Traditional brute force approach

8. Each core is over- provisionedHowever, there is another way . . .

9. Bulldozer: Two Strong Threads Hyperthreaded, single-core chip “Bulldozer” Fetch Fetch Decode Decode IntegerScheduler IntegerScheduler IntegerScheduler FP Scheduler FP Scheduler Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline CORE 1 128-bitFMAC 128-bitFMAC Pipeline Pipeline Pipeline Pipeline 128-bitFMAC 128-bitFMAC L1 DCache L1 DCache L1 DCache Shared L2 Cache L2 Cache

10. DedicatedComponents Shared at the module level Shared at the chip level Sharing Resources Fetch The Bulldozer architecture has shared and dedicated components The shared components: Help reduce power consumption Help reduce die space (cost) The dedicated components: Help increase performance and scalability Bulldozer dynamically switches between shared and dedicated components to maximize performance per watt Decode FP Scheduler IntScheduler IntScheduler Core 1 Core 2 L1 DCache L1 DCache 128-bit FMAC 128-bit FMAC Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Shared L2 Cache Shared L3 Cache and NB

11. Building a Bulldozer-Based Chip Fetch Decode IntScheduler IntScheduler FP Scheduler Shared L3 Cache and NB Integrated Memory Controller Integrated Northbridge Controller Each chip is composed of multiple bulldozer modules Module divisions are transparent to shared hardware, operating system or application The modular architecture speeds chip development and increases product flexibility

12. Bulldozer Summary “Bulldozer” Bulldozer is the next generation of AMD high-performance processor core technology This new core is a completely new design from the ground up Bulldozer will be utilized in client and server designs in 2011 AMD delivers 33% more cores and an estimated 50% increase in throughput in the same power envelope as Magny-Cours* Fetch Decode IntegerScheduler IntegerScheduler FP Scheduler Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline Pipeline 128-bitFMAC 128-bitFMAC L1 DCache L1 DCache Shared L2 Cache *Based on internal AMD modeling using benchmark simulations

13. Two x86 Cores Tuned for Target Markets Mainstream Client and Server Markets “Bulldozer” Performance & Scalability Low PowerMarkets Small Die Area Cloud Clients Optimized “Bobcat” Flexible, Low Power & Small

14. Bobcat Design Goals A small, efficient, low power x86 core Excellent performance Synthesizable with small number of custom arrays Easily Portable across process technologies

16. Out-of-order execution engine

17. Synthesizable / Easy to Reuse

18. Complete ISA support

19. SSE1-3 and virtualization

20. Estimated90% of today’s mainstream performance in less than half of the silicon area*

21. 2011 / notebook APU / “Ontario”L1 Icache Fetch Decode IntScheduler FP Scheduler I-Pipe I-Pipe Ld-Pipe St-Pipe A-Pipe M-Pipe L1 DCache L2 Cache *Based on internal AMD modeling using benchmark simulations

22. Bobcat Core Overview Advanced Micro-architecture Dual x86 Decode Advanced Branch Predictor Full OOO instruction execution Full OOO load/store engine High Performance Floating Point AMD64 64-bit ISA SSE1,2,3, SSSE3 ISA Secure Virtualization 32kb L1s Low Power Design Power Optimized Execution Micro-architecture that minimizes data movement and unnecessary reads Clock gating, Power gating System Low Power States Small Core Area efficient balance of high performance and low power ICACHE L2 Bobcat Low Power Core Fetch BU Decode FP Scheduler Address Scheduler Integer Scheduler A Pipe M Pipe I Pipe Store Pipe I Pipe Load Pipe DCACHE

24. High-speed bus architecture

25. Shared, low-latency memory model

26. Single die designSystem Memory SIMD Engine Array X86 CPU Cores High Performance Bus&Memory Controller Unified Video Decoder Platform Interfaces

27. Bobcat Summary Bobcat is the CPU engine for AMD’s first APU Estimate 90% of the performance of AMD’s current mainstream notebook CPU in less than half the area and a fraction of the power* Highly portable across designs and manufacturing technologies Sub-one watt capable core *Based on internal AMD modeling using benchmark simulations

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