The flexible and easy way to handle your memories in SOC

1. Elsip
Adam Edström CEO
Bengt Edlund Sales Director
February 2013
© Elsip 2012. Elsip non-confidential

2. What we do
Software Defned
Data Management
for Many-core SoC Designs
Solution:
DME = Data Management
Engine

3. What’s DME ?
Scalability
Distributed Shared
Memory private/shared memory
Virtual-to-Physical
translation DMA
DME
Different Privilege
Other specific functions
setting
Synchronization Data Shuffling;
Stride Access;
Transactional Ordering;
Directory of Cache Coherency;
Dynamic Memory Allocation
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4. What’s DME?
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5. Why choose DME?
DME supports centralized shared memory (CM) and distributed shared memory (DSM).
For medium and large system, we prefer to use DSM structures, since centralized
memory has already become a bottleneck. Memories are preferrably distributed,
featuring good scalability and less delay of memory access.
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6. Why choose DME
Processor 1 Processor2
Cache Cache
Network-on-Chip (NoC) Memory
DDR controller
Custom IP
DDR Memory
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7. Why choose DME
Processor1 Processor2
Cache Cache
Interface Interface Local
NI modules in DME
DME P1 M4 Memory
are designed to DME P1 M2 Local
support Standard Memory NI
bus interface, e.g. NI We support:
AHB,APB,AXI, OCP 1. common bus protocol,
easy to integrate into
existing system;
Network-on-Chip (NoC) 2. configurable for different
DME can perform as
data formats;
a bridge connecting
different IPs with
Network
NI NI
DME P1 M2 DME P1 M0
(Local
Interface DDR-Interface
Memory)
DDR controller
Custom IP
DDR Memory
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8. DME Product
DME comes in three flavours
P1 M0 – DME Light – Small footprint, low power,
for memory access and similar standard tasks
P1 M2 – DME Flex – Programmable, fully featured
for maximum flexibility and customization
P1 M4 – DME Flex Plus – Programmable, fully
featured, with maximum performance
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9. DME Product
DME P1 M0 – DME Light
DME
Interconnect-
IP IP-Interface Interconnect
Interface
Feature list:
Transaction Scheduler
1.DSM(distributed shared memory)
2.Private|Shared division
3.Synchronization
4.Privilege level setting (3/2013)
Memory Interface Crossbar
5.IP interface support (AHB,APB) (4/2013)
6.Interconnection interface support (AHB,APB)
(4/2013)
Local Memory Local Memory Local Memory Local Memory
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10. DME Product
DME P1 M2
Data M anagement Engine
Interconnect
CPU CPU Interface Interconnect
Interface
Feature list:
Transaction Scheduler
h
1.DSM(distributed shared memory)
t
a
p
s
2.Private|Shared division
M ini- M ini - s
a
processor processor p
y
3.V2P
B
4.Synchronization
5.Privilege level setting (3/2013)
M emory Interface Crossbar
6.IP interface support (AHB,APB) (4/2013)
7.Interconnection interface support (AHB,APB)
Local Local (4/2013)
M emory M emory
8.DMA-1, DMA-2 (3/2013)
9.Message passing (4/2013)
10.micro-programming 10

11. DME Product
DME P1 M4
Data M anagement Engine
Interconnect
CPU CPU Interface Interconnect
Interface
Feature list:
Transaction Scheduler
h
t
1.DSM(distributed shared memory)
a
p
M ini- M ini - M ini - M ini - s
s
2.Private|Shared division
a
processor processor processor processor p 3.V2P
y
B
4.Synchronization
5.Privilege level setting (3/2013)
M emory Interface Crossbar
6.IP interface support (AHB,APB) (4/2013)
Local Local Local Local
7.Interconnection interface support (AHB,APB)
M emory M emory M emory M emory (4/2013)
8.DMA-1, DMA-2 (3/2013)
9.Message passing (4/2013)
10.micro-programming 11

12. DME Planned Features
Features
AXI Q2 2013
DMA-3 Q2 2013
Striding access Q2 2013
Data shuffling Q2 2013
SystemC Model, SIMICS Model Q3 2013
Transaction ordering support (memory consistency) Q3 2013
Dynamic memory allocation Q4 2013
OCP Q4 2013
Directory based cache coherence On Demand 12

13. DME Configuration Tool
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14. Application Example: H.264 decoder
Task
P1 P2 P3 Pn
Distributor
ITRANS/ INTRA
ENTROPY DEQUANT PREDICTION
P1 P2 P3 P4 P5 P6
Load Private Shared
Store
Mem Mem
3 Private Shared
NODES MEM MEM MEM MEM MEM MEM
Mem Mem
Private Shared
Mem Mem
P7 P8 P9 P10 P11 P12
12
NODES
Private Shared
MEM MEM MEM MEM MEM MEM Mem Mem
with DME based on distributed shared memory without DME based on centralized memory
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15. Demonstrator Performance
Performance(fps)
77
75 with DM E
51 QCIF(176x144)
50
25 without DM E
25 30 31
24 20 with DM E
13 CIF(352x288)
6 without DM E
7 7
3 6 9 node
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16. Applications
The DME is useful for many-core SoCs in:
 Video, signal and network processing
 Cloud computing
 Industrial automation
 Set-top boxes
 Scientific computing
 Solid state disks
 Other high-end embedded applications
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17. DME Features
Note: Perceived value is based on early customer input, and is application dependent.

18. Evaluating the DME
For evaluation of the DME, Elsip offers:
 Introduction Booklet
 DME Application Development
Package, with API libraries
 C++ Model
 SIMICS Model
 Compiled IP Model
 User manual
 Demonstrator
 On-site and off-site support

19. Roadmap
Looking into the future, other IP we’re working on
include:
Packet- and Circuit-switched NoCs (Circuit-switched
can be faster than packet-switched for
telecom/datacom applications)
DRRA - Dynamically Reconfgurable Resource Array
(reconfgurable on bus level, better silicon usage than
FPGA)

20. Thank you!
Please go to
www.elsip.se
for more information

21. The founders
Axel Jantsch, CTO. Professor, KTH Electronic Systems since
2002. 20+ years of research, primarily within NoC and SoC.
200+ scientific papers published. Visiting professor of Fudan
University in PRC and Cantabria University in Spain
Ahmed Hemani. Professor, KTH, focus on high-level system
integration, design automation, NoC, asynchronous circuit,
configurable system. Industrial experience from NSC,
NXP/Philips, ABB, Ericsson, Newlogic, Synthesia and
Spirea (co-founder).
Zhonghai Lu: Professor, KTH, expert in SoC and NoC.
Reviewer of 14 international periodicals. Principal
investigator of Intel, dealing with future nuclear processor
chip frame.
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22. Contact
Sales Director Bengt Edlund
Mail: bengt@elsip.se
Phone: +46 708 722 800
CEO Adam Edström
Mail: adam@elsip.se
Phone +46 702 579 734
Address: c/o SICS, PO Box 1263, SE16429, Kista, Sweden
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23. Some ELSIP Milestones
• Founded by professors Axel Jantsch, Ahmed Hemani
and Zhonghai Lu at the Royal Institute of Technology in
Stockholm 2011
• Received initial funding from Vinnova
• Commercial launch when Adam Edström (CEO) and
Bengt Edlund (Sales Dir) joined the company Sept 2012
• Established subsidiary Memcom in Shanghai March
2012, PRC, with Zhonghai Lu as CTO and Zhuo Zou as
CEO. Received initial funding from Wuxi government.
• Cooperation with Fudan-Wuxi Institute, Shanghai, PRC
• Selected by SICS, the Swedish Institute of Computer
Science, as member of SICS Startup Accelerator
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