4. Confidential4
Outline
Market Trend & Industry Benchmark
KEY Innovative Package Solutions
• Cu Pillar Bump
• 3/2.5DIC
• SiP
• Fan-Out WLP
Technology Challenge and Opportunity
• Scale Down and Thin Down
• Visible Defect
• Invisible Defect
• Special Inspection
Conclusion
5. 305
495
722
1,405
+62%
+46%
0
400
800
1,200
1,600
2010 2011 2012 2016
+0%
+25%
+50%
+75%
+100%
Smartphone
YoY
W/W Smartphone Shipment & FCST to 2016
Shipment (M of Units)
2012~2016
CAGR
+18%
19
72
128
283
+279%
+78%
0
80
160
240
320
2010 2011 2012 2016
+0%
+100%
+200%
+300%
+400%
Tablet
YoY
W/W Tablet Shipment & FCST to 2016
Shipment (M of Units)
2012~2016
CAGR
+22%
Application
Production Units (K) CAGR
2011 2012 2013 2014 2015 2016 2017 2012~17
Server
=> High End
603 715 684 734 736 772 803 2.4%
Server
=> Low End
8,922 8,957 9,254 9,518 9,940 10,360 10,730 3.7%
Subtotal 9,525 9,672 9,938 10,252 10,676 11,132 11,533 3.6%
W/W Server Shipment & FCST to 2017 (for Networking)
Source : IDC (phone & tablet), Gartner (server), Mar. 2013
Mobile Devices and Networking Lead the Growth of Electronics
5
6. Tablet Market Share by Shipment
36.9%
13.4%
28.5%
Apple
Samsung
Amazon
Asus
Brand - China
Others
2nd Tier &
White Brand
9.5%
6.1%3.9%
1.7%
2nd Tier &
White Brand
1Q’2013
Source : IEK(Jun’13)
Smartphone Market Share by Shipment
Quad Core
SAMRT Phone/ Tablet Market Share
6
Country 2013 Unit Shipments 2013 Market Share 2017 Unit Shipments 2017 Market Share 2017/2013 Growth
1. China 301.2 32.8% 457.9 30.2% 52.0%
2. USA 137.5 15.0% 183.0 12.1% 33.1%
3. United Kingdom 35.5 3.9% 47.5 3.1% 33.8%
4. Japan 35.2 3.8% 37.7 2.5% 7.1%
5. Brazil 28.9 3.1% 66.3 4.4% 129.4%
6. India 27.8 3.0% 155.6 10.3% 459.7%
Others 352.5 38.4% 568.1 37.5% 61.2%
Total 918.6 100.0% 1516.1 100.0% 65.0%
TOP 5 Countries Smartphone Shipments and Market Share, 2013 and 2017(Unit in Million)
OCTA Core
Source: IDC, March, 3Q13
Wire Bond
FCCSP
PoP
(Package on Package)
6
7. NOW
Thinner & Lighter Form Factors,
but Low CostOutstanding
Battery Life
Better
Performance
Smartphone Evolution
Smartphone
9.3mm 7.6mm
140g 112g
Mobile Phone is going for several KEY features, including longer battery
life, better performance with more functions, and small form factors
(thinner & lighter), but low cost. It bring a lot of package & technology
challenges !!!
7
8. •CuBOL
•Exposed Die Molded
•Mold Laser PoP
•HBW(High bandwidth) PoP
•Tablet PC
•Smart Phone
•UltraBook
•Wearable Devices
•Cloud Computing
•4G LTE
•Windows 8
•Bandwidth
•Layout Density
•Thermal Dissipation
•Small Form Factor
•Cost Benefit
•Wafer Thinning (25um)
•Ag wire
•TCNCP
•Panel Fan-Out
•TSV Interposer
•Embedded Passive Sub.
•Coreless Sub.
•ETS/MIS(Embedded Trace)
•20/16/14nm Wafer Nodes
•Cu pillar bump
Request for
Wafer Fab & Bumping
Interposer & Substrate
Assembly - Front End
Assembly - Back End
Market Focused Enabling Technology
Confidential
SEMI Growth Drivers IC Packaging Solutions
>>> SPIL is focusing on KEY low cost technologies for SEMI Growth Drivers.
•CuBOL
•Exposed Die Molded
•Mold Laser PoP
•HBW(High bandwidth) POP
•Tablet PC
•Smart Phone
•UltraBook
•Wearable Devices
•Cloud Computing
•4G LTE
•Windows 8
•Bandwidth
•Layout Density
•Thermal Dissipation
•Small Form Factor
•Cost Benefit
•Wafer Thinning (25um)
•Ag wire
•TCNCP
•Panel Fan-Out
•TSV Interposer
•Embedded Passive Sub.
•Coreless Sub.
•ETS/MIS(Embedded Trace)
•20/16/14nm/ Wafer Nodes
•Cu pillar bump
Request for
Wafer Fab & Bumping
Interposer & Substrate
Assembly - Front End
Assembly - Back End
8
(Low Cost Enabling Technology)
9. Confidential9
Product Application
Technology Launch Pipeline
2014 2015 2016~2017
SMART Phone/ Tablet PC
Application Processor;
Baseband;
Connectivity
PMIC
PA
IoT & Wearable Devices
Connectivity
MCU
Memory
MEMS
Computing
Network
GPU
FPGA
Packaging Technology Overview(Focus on high growth products)
Available On-going Candidate
2.5D PoP
(Low Cost Interposer)
PoP Memory
HBW PoP
ePoP
BD-PoP
Panel FO
FO-MCM
EMI-SiP
(Partition shielding)
SiP
(Stack Die on Passives)Antenna in SiP
Large FCBGA
(60x60/65x65/75x75mm)
MCM 2.5DIC
(Low Cost Si-interposer)
MCM 2.5DIC
(Org-interposer)
FO-PoPHBW PoP
(Cu Stud)
Large FO-MCM
MCM 2.5DIC
(Si-interposer)
IC IC
2.5D PoP
(without Interposer)
Photonics Integrate
FO-SiP
10. Confidential10
Smart phone & Tablet devices are big volume growth in the past years, but observe
the wearable & IoT devices (w/ connectivity functions) will become a mainstream in the
near-term future.
Tablet Wearable IoT
HBW PoP Fan-Out 2.5D ICSiP
Thermal DissipationPackage Warpage CPI issue
Applications:
Challenges:
Smart Phone
Solutions:
Networking
Si-Photonics
Advanced Packaging Technology
11. Confidential11
Outline
Market Trend & Industry Benchmark
Key Innovative Package Solutions
• Cu Pillar Bump
• 3/2.5DIC
• SiP
• Fan-Out WLP
Technology Challenge and Opportunity
• Scale Down and Thin Down
• Visible Defect
• Invisible Defect
• Special Inspection
Conclusion
12. CuFCBGA
(Cu pillar bump)
ED-CuFCCSP
(Exposed Die+Cu pillar bump)
Advanced Wire Bonding
(Cu wire/ Ag wire)
Wafer Level Package
Fan-In
LGA /QFN
WB FC die
WB die
WB
S
M
D
Substrate
FC die
LGA /QFN
WB FC die
WB die
WB
S
M
D
Substrate
FC die
LGA /QFN
WB FC die
WB die
WBWB
S
M
D
Substrate
FC die
SiP Module
WWW.SPIL.COM.TW
Fan-Out
Fan-out Area
HBW memory PoP
(High bandwidth)
ED-CuFC-ePoP
(Enhanced PKG on PKG)
Laser DrillLaser DrillLaser Drill Exposed Die
Trace Embedded
Package
MISBGA
(Molded Interconnection System)
ETS
(Embedded Trace Substrate)
3D-IC
Top die
TSI
Substrate
Substrate
DRAM
DRAM
DRAM
DRAM
Top die
TSI
Substrate
Cu Pillar
12
13. << Fine Pitch and High Power Solution >>
Benefits of Cu Pillar+B.O.T.
Benefits:
• Lead free solution for RoHS requirement
• High current and EM capability
• Fine pitch (high I/O density) with B.O.T. (Bump On Trace)
Cu Pillar Bump
SnAg
Bump Pitch: 180um 150um 130um 100um 80um 60um 40um
Solder Bump
CuBOT
13
14. Compared w/ solder bump, two benefits can achieve 20~30% cost down benefits
a. wafer : Increase 70% die quantity per wafer !! (Wafer utilization up)
b. Assembly :Sub cost down 20~30%
Category
Lead Free
Bump
Cu Pillar
Bump
Remark
Front
End
Die Size
(mm)
12*12 8.6*10.7
Die Area Shrink
CPW: 390->680 (increase ~70%
#die in 12” wf) Save DIE COST
Bump Pitch
(um)
180 90 Shrink 50%
Back
End
Sub Layer 2/2/2 L 1/2/1 L Cost down ~20-30% of substrate
cost
Pre-Solder Y N
PKG Information
PKG Type : EHS-FCBGA 35*35
Total cost down 20~30%
Benefits of Cu Pillar+B.O.T.
14
15. CuFCBGA
(Cu pillar bump)
ED-CuFCCSP
(Exposed Die+Cu pillar bump)
Advanced Wire Bonding
(Cu wire/ Ag wire)
Wafer Level Package
Fan-In
LGA /QFN
WB FC die
WB die
WB
S
M
D
Substrate
FC die
LGA /QFN
WB FC die
WB die
WB
S
M
D
Substrate
FC die
LGA /QFN
WB FC die
WB die
WBWB
S
M
D
Substrate
FC die
SiP Module
WWW.SPIL.COM.TW
Fan-Out
Fan-out Area
HBW memory PoP
(High bandwidth)
ED-CuFC-ePoP
(Enhanced PKG on PKG)
Laser DrillLaser DrillLaser Drill Exposed Die
Trace Embedded
Package
MISBGA
(Molded Interconnection System)
ETS
(Embedded Trace Substrate)
3D-IC
Top die
TSI
Substrate
Substrate
DRAM
DRAM
DRAM
DRAM
Top die
TSI
Substrate
SiP
15
16. Wearable Devices
(BT/ WiFi Connect with Smartphone)
Pebble-Smart Watch
RF Module
(Bluetooth Controller)
Google Glass
WiFi +BT Module
Google Talking Shoes
(Accelerometers, gyroscopes and pressure sensors
will integrate on the shoes)
Rhythm band BT Audio Module
BT Module
16