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Physical design

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VLSI Physical Design
Data preparation, import design, floorplan
Power planing
power ring, core power, IO power ring, pad, bump creattion.

Physical Verification.

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Physical design

  1. 1. VLSI Physical Design
  2. 2. Table of Contents 1. Introduction to VLSI 2. Design Flow in VLSI 3. Physical Design Flow 4. Data Prepare 5. Floorplan
  3. 3. Introduction to VLSI Small scale integration (SSI) 1 – 10 gates Medium Scale Integration (MSI) 10 – 100 gates Large Scale Integration (LSI) 100 – 1000 gates Very Large Scale Integration (VLSI) 1000 – 100000 gates Ultra High Scale Integration (ULSI) > 100000 gates
  4. 4. Design Flow in VLSI ASIC Physical Design Design Specification Behavioral Description RTL Description Logical Synthesis/ Timing Verification/ STA Custom Design Floor planning Placement & Routing STA / Physical Verification / DFM GDS  package  Silicon Chip On Board Functional Verification
  5. 5. Design Flow in VLSI ASIC
  6. 6. Physical Design Flow Data Prepare Read Design Floorplan Physical Design Placement CTS Route STA,DRC,LVS & DFM GDS
  7. 7. VlSI Chip Design Flow 7 Design Import Floor Planning Placement Trial Route & Optimization Clock Tree Synthesis Post CTS Optimization Detailed Routing Postroute Opt. Physical Verification Architectural Design RTL Design RTL Verification DFT Insertion Logic Synthesis Formal Verification Post Synthesis STA Floorplanning and placement CTS and routing DRC and Post layout STA Physical Design Flow Tape out Tape Out
  8. 8. What is Physical Design ?  Transformation of a circuit design into physical representation for manufacturing  The circuit design is described through a netlist.  The end product from a physical design is a layout which passes  Design Rule Checks  Connectivity Checks  Timing Analysis Checks  Power Analysis Checks  The layout data is sent to foundry to generate masks and fabrication
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  10. 10. Table of Contents 1. Introduction to VLSI 2. Design Flow in VLSI 3. Physical Design Flow 4. Data Prepare 5. Floorplan
  11. 11. Data preparation 1) Verilog Netlist 2) Constraints 3) Timing library 4) Physical library 5) - timing 6) Tech info Design Data Netlist SDC Logical Library .libs .db Physical Library CEL (GDS) FRAM (LEF) Tech Info Tech file(.tf) TLU+ files Map file Cap table
  12. 12. Constraints Set default fanout, trans and cap for all the inputs and outputs Read_sdc Clocks definition, IO delays, FP, MCP Set max trans and cap for clocks Read scan and MBIST related constraints Set operating conditions single, OCV or bc_wc
  13. 13. Constraints: Commands  Clocks  create_clock  Input Delay  set_input_delay  Output Delay  set_output_delay  Output Load  set_load  Input Drive Resistance  set_driving_cell  False Paths  set_false_path  Multicycle Paths  set_multicycle_path  Operating Conditions  set_operating_conditions  Wireload Model  set_wire_load
  14. 14. Single, bc_wc & OCV Timing paths consist of a series of cells and nets connected together. The delays of the cells and nets represent the amount of time it takes for a signal transition (or edge) to propagate across those cells or nets. Consider buffer cells U1 and U2 connected together by net n1, as shown in Figure 1: Figure 1: Buffer To Buffer Example Circuit The rising cell delay across cell U1 and the rising net delay across net n1 can be shown graphically by the waveforms in Figure 2:
  15. 15. Single, bc_wc & OCV Setup paths are paths where the checked signal edge must be stable for some time (the setup time) before the capturing edge. In simple terms, this makes sure the launched edge gets to the capture point soon enough. Setup paths include normal data-to-clock setup paths, the assertion of data-to-data and clock gating checks, and asynchronous recovery checks. For proper analysis, setup paths must check the latest launching edge against the earliest capturing edge. Hold paths are paths where the checked signal edge must be stable for some time (the hold time) after the capturing edge. In simple terms, this makes sure the launched edge does not arrive at the capture point too soon. Hold paths include normal data-to-clock paths, the deassertion of data-to-data and clock gating checks, and asynchronous removal checks. For proper analysis, hold paths must check the earliest launching edge against the latest capturing edge.
  16. 16. Single, bc_wc & OCV set_operating_conditions -analysis_type <type> Single: The single analysis mode analyzes a single operating corner. This goes back to the first releases of Design Compiler over a decade ago, when it was the only available analysis mode. In the single mode every timing arc is evaluated once using the "max" stimuli:  Max lumped capacitive loads are used if they are annotated  Max pin loads or receiver model characteristics are always used  Max slew propagation is performed at slew merge points Both setup and hold paths use the computed max-delay arcs. Setup paths use the longest path through these arcs for launch, and the shortest path for capture. Hold paths use the shortest path through the arcs for launch, and the longest path for capture
  17. 17. Single, bc_wc & OCV BC_WC: The bc_wc analysis mode analyzes two operating corners simultaneously. In the bc_wc mode every timing arc is evaluated twice, once using the "max" stimuli and once using the "min" stimuli:  Min lumped capacitive loads are used for the min arcs, and max lumped capacitive loads are used for the max arcs (if annotated)  Min pin caps or receiver models are used for the min arcs, and max pin caps or receiver models are used for the max arcs  Min slew propagation is performed at the slew merge points for min delays, and max slew propagation is performed at slew merge points for max delays In the bc_wc mode, the two corners can represent two PVT (process/voltage/temperature) corners which cannot physically coexist at the same time. For example, the min corner could be configured at 0 °C and 1.3 V, while the max corner could be configured at 100 °C and 1.1 V. The two corners in bc_wc mode represent two completely independent PVT corners.
  18. 18. Single, bc_wc & OCV Setup paths use the longest path through the max-delay arcs for launch, and the shortest path through the max-delay arcs for capture. Hold paths use the shortest path through the min-delay arcs for launch, and the longest path through the min-delay arcs for capture. In other words, the bc_wc analysis mode only checks setup at the max corner, and hold at the min corner. It is important to remember that setup paths are not checked at the min corner, and hold paths are not checked at the max corner. This could miss timing violations due to differences in how the launch and capture paths track the PVT difference between the corners.
  19. 19. Single, bc_wc & OCV OCV: The on_chip_variation analysis mode analyzes a single operating corner while considering the variation in arc timing which can exist within that corner. Just as in bc_wc mode, in on_chip_variation mode every timing arc is evaluated twice, once using the "max" stimuli and once using the "min" stimuli:  Min lumped capacitive loads are used for the min arcs, and max lumped capacitive loads are used for the max arcs  Min slew propagation is performed at the slew merge points for min delays, and max slew propagation is performed at slew merge points for max delays
  20. 20. Timing Parameters Used For Setup Checks analysis mode setup launch path setup capture path single slowest path through max-delay arcs, single operating condition, no derating fastest path through max-delay arcs, single operating condition, no derating bc_wc slowest path through max-delay arcs, worst-case operating condition, late derating fastest path through max-delay arcs, worst-case operating condition, early derating on_chip_variation slowest path through max-delay arcs, worst-case operating condition, late derating fastest path through min-delay arcs, best-case operating condition, early derating
  21. 21. Timing Parameters Used For hold Checks analysis mode hold launch path hold capture path single fastest path through max-delay arcs, single operating condition, no derating slowest path through max-delay arcs, single operating condition, no derating bc_wc fastest path through min-delay arcs, best-case operating condition, early derating slowest path through min-delay arcs, best-case operating condition, late derating on_chip_variation fastest path through min-delay arcs, best-case operating condition, early derating slowest path through max-delay arcs, worst-case operating condition, late derating
  22. 22. Timing derate set_timing_derate -early | -late [-rise] [-fall] [-clock] [-data] [-cell_delay] [- cell_check] [-net_delay] [-static] [-dynamic] [-scalar | -variation | - aocvm_guardband | -pocvm_guardband] [-pocvm_coefficient_scale_factor] [- increment] derate_value object_list
  23. 23. Clock Reconvergence Pessimism Removal (CRPR) When launching and capturing clock share common path, the common path min delay and max delay will add additional pessimism to both setup and hold analysis. CRPR can be used to remove this pessimism.
  24. 24. Clock Reconvergence Pessimism Removal (CRPR) As you can see that flop share a common clock but are placed physically at the different places in the same die. Or in other way you can say that Launch clock path and capture clock path share a common segment in the clock tree till the point know as "common point" (in above fig you can see that "common point" is written as "The clock path common to both flops till this point"). The 2 clock path diverse from that point.
  25. 25. Basic Terminology in Physical Design Design: A circuit that performs one or more logical functions. Cell: An instance of a design or library primitive within a design. Port: The input or output of a design. Pin: The input or output of a cell. Net: A wire that connects ports to ports or ports to pins. Clock: A timing reference object to describe a waveform for timing analysis. Logical Libraries: Logical libraries are libraries which provide Timing and functionality information for all standard cells (like AND, OR, Flipflops) Timing information for Hard Macros (IP, ROM, RAM) 25
  26. 26. Different views CEL view: The full layout view of a physical structure such as a via, standard cell, macro, or whole chip; contains placement, routing, pin, and netlist information for the cell FRAM view: An abstract representation of a cell used for placement and routing; contains only the metal blockages, allowed via areas, and pins of the cell FILL view: A view of metal fill, which is used for chip finishing and has no logical function, created by the signoff_metal_fill command in IC Compiler. CONN view: A representation of the power and ground networks of a cell, created by PrimeRail or IC Compiler and used by PrimeRail for IR drop and electromigration analysis. ERR view: A graphical view of physical design rule violations found by
  27. 27. Logical Library Provides timing ,power and functionality information for all standard cells. Provides timing , power information for hard macros (Hard IP, ROM, RAM, ..) Logical information's are provided by .lib's or .db files Physical Library ( Milkyway reference Libraries) Contains physical information of standard cells and hard macros. Physical information's are provided in the form of LEF (FRAM), GDSII (CEL) views
  28. 28. library definition The library definition file (i.e., sc_cadence.lib) is broken into two sections: a header section that defines attributes to be used by all cells in the library, and cell section that has a definition for each cell in the library. A cell’s definition defines attributes about the cell such as pin names, area, functionality, timing, power, etc.
  29. 29. Contents of a Library  Units (V, A, pW, KOhm, nS, etc)  Default parameters  Max transition  Input pin cap  Wireload mode  Operating condition  Max fanout  Nominal Parameters (PVT)  Operating Conditions  Worst Case /Best Case  Scaling factors  K Factors  Wireload Models  Estimate for fan-in, fan-out  Look-up table templates  Cells: all properties & attributes, Delay Tables, Rise/Fall Transition Tables, Power Tables
  30. 30. Wire load model WLM is an estimation of delay, based on area and fanout. It is obsolete technology and after physical synthesis there’s no use of it. Prior to Routing stage, net parasitics and delays cannot be accurately determined. So, to predict delay we need to know the parasitics associated with interconnect/net: Resistance wire_load("45Kto75K") { Capacitance Area of the nets. capacitance : 0.000070; resistance : 0.000042; area : 0.28; slope : 40.258665; fanout_length(1, 40.258865); fanout_length(2, 80.517750); fanout_length(3, 120.776600); fanout_length(4, 161.045450); fanout_length(5, 241.543200); fanout_length(6, 322.070900); fanout_length(7, 402.587600); }
  31. 31. Wire load model  Top: use the WLM for the top module to calculate delays for all modules. Mantravlsi.blogspot.com  Enclosed: use the WLM of the module which completely encloses the net to compute delay for that net. Mantravlsi.blogspot.com  Segmented: if a net goes across several WLM, use the WLM that corresponds to that portion of the net which it encloses only. Mantravlsi.blogspot.com
  32. 32. Wire load model
  33. 33. cell’s definition cell (and2) { area : 434.7; pin(A1) { direction : input; capacitance : 2.141; } pin(B1) { direction : input; capacitance : 1.948; } pin(O) { direction : output; function : "A1 * B1"; } cell (dfr) { area : 4819.5; ff(IQ,IQN) { next_state : "DATA1"; clocked_on : "CLK2’"; clear : "RST3’"; } pin(DATA1) { direction : input; capacitance : 51.289; } pin(CLK2) { direction : input; capacitance : 52.305; } pin(RST3) { direction : input; capacitance : 28.602; } pin(Q) { direction : output; function : "IQ"; }
  34. 34. Lookup table Can either use a 1-dimensional or 2-dimensional lookup table for setup/hold timing. For 2-dimensional table, the two axes are transition time on data pin, transition time on clock pin. Same template used for both setup and hold. lu_table_template(dff3x3) { variable_1: constrained_pin_transition ; variable_2: related_pin_transition ; index_1 {“0.01, 0.1, 2.0”} ; index_2 {“0.01, 0.1, 2.0”} ; For 1-dimensional table, the axis is different depending on setup or hold time. Need seperate templates for setup/hold. lu_table_template(setup_1d) { variable_1: constrained_pin_transition ; index_1 {“0.01 0.1 2.0”} ; For setup time, vary transition time on data input, use a fast transition time for clock lu_table_template(hold_1d) { variable_1: related_pin_transition ; index_1 {“0.01 0.1 2.0”} ;
  35. 35. I/O Pad Specification cell (IPAD_1) { area : 2973.6 ; pad_cell : true; pin ( A ) { direction : input ; capacitance : 85 ; is_pad : true ; } pin ( Y ) { direction : output ; function : "A" ; } } cell (OPAD_1) { area : 2973.6 ; pad_cell : true; pin ( A ) { direction : input ; capacitance : 278 ; } pin ( Y ) { direction : output ; function : "A" ; is_pad : true ; drive_current : 0.05 ; } }
  36. 36. .lib specification
  37. 37. Library Architecture Multi-VT Libraries Library Cell Offerings Transition Time Trade-off Routing Layer Stack Variants Wide Track –Vs– Narrow Track
  38. 38. Library Exchange Format (LEF):: Cell view The LEF file contains layer, via, and macro definitions as in this example. 38 VDD GND A B Y NAND_1 reference point (typical) Dimension “bounding box” Pins Symmetry (X, Y, or 90-degrees) • Direction • Layer • Form LAYER m1 TYPE ROUTING ; WIDTH 0.50 ; END m1 LAYER via TYPE CUT ; END via MACRO NAND_1 FOREIGN NAND_1 0.00 0.00 ORIGIN 0.00 0.00 ; SIZE 4.5 by 12.0 ; SYMMETRY x y ; SITE core ; PIN A DIRECTION input ; PORT LAYER m1 ; RECT 6.4 10.0 6.8 10.4 ; END PIN Y OBS LAYER via ; RECT … RECT ... END NAND_1
  39. 39. 39 Capacitance Table The capacitance table contains routing metal dimensions and properties. It is technology and process-corner dependent. You can get a capacitance table from your foundry or you can generate
  40. 40. TLUPLUS file In Apollo and Astro technology there is a linear capacitance model, where the net capacitance is calculated in terms of capacitance per square user unit of conducting and via layers specified in the Milkyway technology file (or .tf file). To get higher extraction accuracy and still get the runtime benefit, a Table Look- Up model or table, which contains wire capacitance at different spacings and widths, is precalculated and stored in the Milkyway technology file. TLU internally calls capGen, which is normally bundled with Astro and Apollo, to create this table. The Astro and Apollo Linear Parasitic Extraction (LPE) will look up appropriate wire capacitances from the table during the extraction. The grdgenxo command, which is normally bundled with Star-RCXT, is a more accurate engine to create the table than capGen. After processing and attaching the grdgenxo-generated capacitance table to the Milkyway database, the Astro LPE/TLUPlus will be able to extract the net capacitances using the same extraction engine but different CapTable compared to LPE/TLU. Check_tlu_plus_files TLU+ Files ( Cap Tables) Contains the R and C values for every layer's per unit length.. P&R tool calculates C and R using the net geometry and the TLU+ look-up tables
  41. 41. Layermap files conducting_layers c4b c4 tm1 tm1 metal10 m10 metal9 m9 metal8 m8 metal7 m7 metal6 m6 metal5 m5 metal4 m4 metal3 m3 metal2 m2 metal1 m1 poly p tcn tcn gcn gcn via_layers tv1 tv1 via10 via10 via9 via9 via8 via8 via7 via7 via6 via6 via5 via5 via4 via4 via3 via3 via2 via2 via1 via1 The Mapping File maps the technology file layer/via names to .itf layer/via names.
  42. 42. Library Sanity Checks Logical and Physical library inconsistencies: Missing Cells Missing or mismatched pins Missing CEL or FRAM views Duplicate cell name in the reference libraries
  43. 43. Design preparation
  44. 44. Gate Level Netlist Design Preparation Provides the logical connectivity information of the design. Contains references to standard cells and macros, which are stored in the logical libraries  Uniquifying Netlist Designs with multiple instances having same instance name. P&R tool does not support non-uniquified designs Linking Timing Constraints Communicates the design’s timing intentions to P&R tool.
  45. 45. Linking the design
  46. 46. Netlist: Combo loops Assign statements Floating inputs Multi driven nets Constraints: Design Sanity Checks All flops are clocked. No unconstrained paths Input delays, Output delays. Input slew, Output load
  47. 47. Table of Contents 1. Introduction to VLSI 2. Design Flow in VLSI 3. Physical Design Flow 4. Data Prepare 5. Floorplan
  48. 48. Floor planning Die Size Estimation/ Die Area Creation Core Area Initialization Limitations / Types Row configuration Cell orientation Flip chip technology IO & Bump Placement Macro Placement Flight-lines (Fly-lines) Placement Blockage Routing Blockages Evaluating the macro placement Congestion Analysis Timing Analysis
  49. 49. Floor planning cont…. Power planning and management Core Power Ring Vertical and Horizontal Straps Pad Power Ring PAD to core ring power strap Power rails Power Planning Equations Some Power Planned Chip Examples
  50. 50. Displaying the Design after Design Import 50 Hard/Custom Blocks Core Area Pink module guides consisting of standard cells
  51. 51. Die Size Estimation/ Die Area Creation Resources
  52. 52. Die Size Estimation/ Die Area Creation Die Size depends on Netlist Area Utilization Aspect Ratio Height / width Netlist Area is the sum of : Standard Cell area Hard Macro Area IO Cell area IO Cell area Total Utilization = Netlist Area/ Total Die Area Aspect Ratio= Horizontal Routing Resources / Vertical Routing Resources
  53. 53. Die Size Estimation/ Die Area Creation 4.2.2 Die size calculation: Total gate count of the design = Tg ( 2 input NAND gate equivalents) 2 input nand gate area = An Core area for 70% row utilization = Tg  An = (Tg  An)  (0.7) Hard macros area = Am Total area(Ac) = Am  (Tg  An)  (0.7) Core edge = Sqrt (Ac) IO cell dimensions = W  H Core to IO distance(d) = total width of power ring + spacing between rings Die edge = Core edge + 2(d + H)
  54. 54. Die Size Estimation/ Die Area Creation Example: Standard cell area 5000 sq um Macro area 2000 sq um
  55. 55. Core Area Initialization Core area depends on: standard cells and hard macros. Aspect ratio (Height/Width). Target Utilization. Standard cell rows Height of the row will be same as the height of standard cell.
  56. 56. Row configuration Row and site are same All the standard cells height will be integer multiple of the row Flipped row are used for P/G
  57. 57. Row configuration Flipped row to share common power and ground Confidential: Authorized Distribution Only
  58. 58. Cell orientation & information Orientations :  The default orientation is "vertically and face up" - N (North). Rotate by 90deg clockwise to get E, S and W.  flip to get FN, FE, FS and FW. The cell placement format represents (x,y) placement of cells (may be undefined for some cells).  optional fixed status and optional spatial orientation of each cells. Files in placement format have extension .pl and are to be used with standard cell layuot (.scl) files and [multi-file] specifications of hypergraph with pins.
  59. 59. Standard Cell Placement
  60. 60. Flip-Chip Technology Flip-chip technology provides higher levels of integration and higher packaging densities. a Flip chip is direct electrical connection of face-down (flipped) electronic components onto substrate, board, or carrier by the conductive bumps Pads are placed in a matrix to minimize chip size. Used for very large designs Eliminating packages and bond wires reduces the required board area by up to 95%, and requires far less height. Weight can be < 5% of packaged device weight performance, flexibility, reliability, and cost are advantageous over other packaging methods
  61. 61. Flip-Chip Technology With flip-chip technology The die is flipped upside-down and attached directly to the substrate using solder bumps. This method provides electrical connections with minute parasitic inductance and capacitance. Some percentage of the top metal layer is not available for signal routing. Signal connections are required from metal layer 1 (where the pad cells are located) to the corresponding bond pads on the top metal layer.  A byproduct advantage of flip-chip is more room for the bond pads.
  62. 62. Flip-Chip Technology The flip-chip package, is an advanced packaging technology and created for higher integration density and larger I/O counts. For the flip-chip applications, typically the top metal or an extra metal layer, called a re-distribution layer (RDL), is used to redistribute I/O pads to bump pads without changing the placement of the I/O pads. Bump balls are placed on the RDL and use the RDL to connect to I/O pads by bump pads. 62
  63. 63. Flip-Chip Technology Recent IC’s place I/O pads (buffers) in the whole area of a die, instead of just placing them along the die boundary. Consequently, this placement results in shorter wirelength, higher chip density, and better signal and power integrity. 63
  64. 64. Flip-Chip Technology After floorplanning the circuit blocks and the I/O buffers, we need to route from the block ports to the I/O pads (chip-level routing), from the I/O pads to the bump pads (package-level routing). 64
  65. 65. IO & Bump Cell Placement Following IOs and bumps are placed Signal IOs & Bumps Power IOs & Bumps Corner Cells Filler Cells Physical-only pads (VDD/GND) that are not part of the input gate level netlist need to be inserted prior to reading io constraints. IO constraints are read in the form of IO file. IO file define IO constraints such as pin/pad location, edge, order.
  66. 66. Problem Formulation A. Package-level Routing : Let Q be the set of I/O pads, and B be the set of bump pads. For practical applications, each I/O pad is assigned to one bump pad. 66
  67. 67. Problem Formulation B. Chip-level Routing : Let P be the set of block ports. The number of I/O pads is larger than or equal to the number of block ports, i.e., |Q| ≥ |P|, and each block port pi can be assigned to only one I/O pad qj . 67
  68. 68.  Basic Network Formulation Bump pad Tile node Intermediate node I/O pad  For a single layer  An edge is constructed between a block port and an I/O pad if the block port is assigned to the I/O pad of the same buffer type.  Each I/O pad connects either to its nearest intermediate node or to its nearest tile node.  And ten type of edges. 68 The Routing Algorithm
  69. 69. IO file format  (iopad (topright (inst name="IOPADS_INST/Pcornerur" ) ) (top (inst name="IOPADS_INST/Ptdspip15" ) (inst name="IOPADS_INST/Ptdspop15" )  ………….. (inst name="IOPADS_INST/Ptdspop09" ) ) (topleft (inst name="IOPADS_INST/Pcornerul" ) ) (left (inst name="IOPADS_INST/Pscanckip" ) (inst name="IOPADS_INST/Pscanenip" )  ………  ) 69
  70. 70. Floorplanning design limitations Core limited design The chip size is limited by the core size Pad limited design  The chip size is limited by the no. of pads in the design. 70 CORE Pad CORE Pad Bond Pads Corner Cells Pad fillers
  71. 71. Floorplan types Flat design Design has only one(top) level of hierarchy Netlist can be flat or hierarchical Contains Hard macros(RAMS) and standard cells Hierarchical design Design has multiple level of hierarchy Netlist can be only hierarchical Contains Softmacros(blocks), Hard macros(RAMS) and standard cells. Soft macros inturn have RAMS and blocks (if reqd) and standard cells 71
  72. 72. Flat design flow Create floorplan cell Place all macros Place macros according to their connectivity preferably around the boundary Power planning P/G rings and straps Create Groups and Regions(Optional) For group of cells which needs to be placed closer together or at a specific location, create groups and regions. Place standard cells congestion driven - if there are no constraints (or) Timing driven - if it has timing constraints 72
  73. 73. Flat design flow:  Synthesize Clocks Create clock trees using buffers to meet skew  Perform timing optimization Fix transition, setup and hold violations  Route the design Global route Detail route Verify design Fix DRC, LVS and ANTENNA errors. 73
  74. 74. Hierarchical design flow: Create floorplan cell Flatten all child instances Design contains Soft macros or blocks, Hard Macros and standard cells Place cells Arrange macros according to their connectivity Pin Optimization Assign pins based on the current floorplan and perform softmacro pin optimization for all blocks and top level Power planning P/G rings and straps and macro/pad preroutes Create Groups and Regions(Optional) For all blocks individually and top level if required. 74
  75. 75. Flat design - Advantages/Disadvantages Better timing as compared to hierarchical design Better chip area as compared to hierarchical design Fewer no of iterations to meet timing closure One p&r engineer can handle the whole chip 75
  76. 76. Hierarchical design - Advantages over flat design Can handle larger designs with Multi-million gates Design is partitioned into multiple blocks, allowing several engineers to work on one design at the same time. provides a modular incremental approach to timing closure  i.e., Allows timing closure for individual blocks which allows timing re-budgeting for other blocks that are not closed yet. Design and signal integrity problems are best solved in hierarchical designs 76
  77. 77. Timing Budgeting: Purpose is to translate chip-level timing requirements of top cell into timing requirements for individual top-level soft macros.  Generate timing delay models for all soft macros  Analyse the timing information and modify the floorplan or block locations accordingly With top level constraints available, the tool allocates budgets to each individual block  If timing violations exists in individual blocks, re-budgeting will resolve it by borrowing/acquiring budgets from other blocks 77
  78. 78. Types of pad and bump designs: In_line pads: Pad size is limited by bondpad width. Normally used for core limited designs Used for smaller designs with less no. of pads. 78 Bondpad Active Pad CORE Pad boundary
  79. 79. Types of pad designs Staggered pads Pad size is limited by active pad width More no. of pads can be accomodated for the same core size. Used for larger designs with high pinouts. No of pads limited by the size of the bondpad. 79 Bondpad Active Pad CORE Pad boundary
  80. 80. Macro Placement Macro Placement is done based on Connectivity information. Macros to IO cells Macro to Macro Macro placement is very critical for congestion and timing Macro placement should result in uniform standard cell area. Macro Placement Requires;  Flyline Analysis  Placement Blockage Channel calculation
  81. 81. Macro placement Read def Place macro manually Check the timing and fly lines Set the orientation
  82. 82. Macro’s Definitions :  SOFT MACRO  A block which is not placed and routed  size and shape could be modified Firm Macro:  Gate level implementation but no physical design  HARD MACRO  A block which cannot be altered  ex: RAM’s, PLL’s  GROUPS  A set of cells and hardmacros which needs to be placed together  Floorplan groups can be created for all softmacros or for 1st level of hierarchy below the top cell or on all levels of hierarchy  REGIONS  Location of the floorplan group can be constrained by assigning groups to cell regions. 82
  83. 83. Initialize floorplan Read def IO placement Create floorplan Create_rectlinear block Derive pg connections Set wiretracks unset_preferred_routing_direction -layer metal1 remove_track -layer metal1 -dir X set_preferred_routing_direction -layer metal1 -dir vertical create_track -layer metal2 -dir Y -coord 0.040 -space 0.080 -bounding_box [list {0 0} [list $fubx $stop_y]]
  84. 84. Create floorplan  create_floorplan [-bottom_io2core distance] [-control_type aspect_ratio | width_and_height | boundary] [-core_aspect_ratio ratio] [-core_utilization ratio] [-flip_first_row] [-keep_io_place] [-keep_macro_place] [-keep_std_cell_place] [-left_io2core distance] [-min_pad_height] [-no_double_back] [-pad_limit] [-right_io2core distance] [-start_first_row] [-top_io2core distance] [-use_vertical_row]
  85. 85. Create Floorplan Place macro Add halo (boundary and macro) Add fib cells Add tap cells Create route guide (create routing blockages) Create power mess Add fiducial cells Insert diodes for I/P ports
  86. 86. Flyline Analysis & Macro Placement
  87. 87. Placed Macros
  88. 88. Placement Blockage Placement blockages are used to reduce congestion around the macros 88
  89. 89. Placement Blockages Hard  A hard blockage prevents the placement of standard cells and hard macros within the specified area during coarse placement, optimization, and legalization. Hard macro Soft  A soft blockage prevents the placement of standard cells and hard macros within the specified area during coarse placement, but allows optimization and legalization to place cells within the specified area. Partial  A partial blockage limits the cell density in the specified area during coarse placement, but has no effect during optimization and legalization. For information about defining a partial placement blockage. Pin  A pin blockage prevents the global router from routing in the specified area, and the pin placer from assigning pins to the area.
  90. 90. Defining Placement Bounds (REGIONS) A placement bound is a constraint that controls the placement of groups of leaf cells and hierarchical cells. It allows you to group cells to minimize wire length and place the cells at the most appropriate locations.
  91. 91. Types of Bounds (REGIONS) Soft move bounds For soft move bounds, the tool tries to place the cells within the specified region; however, there is no guarantee that the cells are placed inside the bounds Hard move bounds For hard move bounds, the tool must place the cells within the specified region. Exclusive move bounds For exclusive move bounds, the tool must place the cells within the specified region and must place all other cells outside of the region.
  92. 92. Finalizing Floor Plan Congestion and Timing Analysis Make sure congestion is under control after macro placement Timing numbers are reasonably good. So that we don't face any issues in routing and timing ahead in the flow. Fix the macro locations so that placement tool will not change the macro locations.
  93. 93. Power Planning
  94. 94. Power Planning Power planning is done to provide uniform supply voltage to all cells in the design. Core Power Management  Core Ring  Core Power/Ground Straps  Standard cell rails I/O Power Management  IO rings are created through:  IO Cell abutment  IO filler cells
  95. 95. Power Planning Core Power Management VDD and VSS rings are formed around the core and macros.  Power straps are created in the core area to tap power from Core Rings.  Standard cell rails are created to tap power from power straps to std cell power/ground pins. I/O Power Management  IO rings for power are established through IO cell abutment and through IO filler cells.  Power rings are formed for I/O cells and trunks are constructed between core power ring and power pads.
  96. 96. Core Power Ring, Stripes & Power Pads 96
  97. 97. Power / Ground Rings and Stripes 97 Design Views Visibility Toolbar Icons Floorplannin g Icons Selectabilit y Pull-Down Menus
  98. 98. IOs ,core ring &power Strap IO ring break
  99. 99. Power Planning You can add power rings and power stripes to connect blocks and cells to the power structures. 99 … Floorplan Power Place…
  100. 100. Add Rings: Basic Tab (Core Rings) 100 •Choose Power – Power Planning – Add Ring. •Core rings follow the contour of the core boundary or the I/O boundary. • You can specify the layers, their widths, their spacing, and the offset. • You can also exclude selected objects, such as blocks that typically have their own power structure. Load the options file that you created earlier.
  101. 101. Add Stripes You can create stripes for power and ground nets by selecting Power – Power Planning – Add Stripes. Options Set configuration Nets – Specify the nets. Layer – Specify the layer to use. Width – Specify the width of the stripes that you want to create. If the number of widths specified is less than number of nets specified, then the last value specified for width is used for the unmatched nets. Spacing – Specify the spacing between pair of the stripes. Set pattern You can define the distance between each stripe set and the number of sets. Stripe Boundary You can specify the target of the stripe by selecting an object for the stripe to connect to, which enables relative power planning. 101
  102. 102. Add Stripes: Spacing Definitions Spacing and Set Pattern Definitions 102 Width a Spacing Width b VDD GND VDD GND Set-to-set distance Boundary offsets are measured from core boundary edge. You can improve routability and availability of routing tracks by selecting the width and spacing as it relates to the routing grid.
  103. 103. Add Stripes: Spacing Definitions
  104. 104. Power Planning methodology Power/Ground Pads Number of the core power pad required for each side of the chip = total core power / [number of side* core voltage*maximum allowable current for a I/O pad] Core Ring current (mA) = core power / core voltage Core PG ring width = (Total core current) / (No. of sides *  maximum current density of the metal layer used (Jmax) for PG ring) Similar calculations are done for core power straps (width, pitch)  based on EM and IR requirements.
  105. 105. Power Network Analysis To analyze power network : Robustness Voltage (IR) drop Electro Migration Adjust power network to solve reported issues
  106. 106. IR Drop and EM Analysis IR Drop Drop happens in supply voltage when traverses through the power network. Depends on : Power requirement of the design Power network structure. Electro Migration (EM) Current density checks on power network Depends on: Design current requirement Width of power meshes.
  107. 107. IR Drop Causes … Improper placement of power/ground pads. Insufficient core ring, power strap width. Lesser no of power straps. Lesser number of power pads. Missing vias.
  108. 108. Power Planning Recap Power planning is done to provide uniform supply voltage to all cells in the design. Core Power Management Core Ring Core Power/Ground Straps Standard cell rails I/O Power Management IO rings are created through: IO Cell abutment IO filler cells
  109. 109. General Notations Of The Pwr/Gnd # Digital Pwr/Gnd => VDD/VSS # Analog Pwr/Gnd => AVDD*/AVSS* # IO Pwr/Gnd => IOVDD*/IOVSS* # Check the Data sheets for more details
  110. 110. References Cadence Encounter Synopsis ICC Prime time Google.com

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