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Intel core i3, i5, i7 , core2 duo and atom processors

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Intel core i3, i5, i7 , core2 duo and atom processors

  1. 1. Introduction to recent Intel Processor Microarchitecture and Brand Processor Families By : Fady Morris Milad May 25, 2013
  2. 2. What aspects will we compare processors according to ? • Instruction Set Architecture(ISA) : is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O. An ISA includes a specification of the set of opcodes (machine language), and the native commands implemented by a particular processor. Example : x86, x86-64, MMX • Microarchitecture : the way a given instruction set architecture (ISA) is implemented on a processor examples : P6, NetBurst, Core, Nehalem, Sandy Bridge
  3. 3. What aspects will we compare processors according to ? • Marketing Names : Example : Pentium, Core2Duo, Core i3, i5, i7 • Fabrication Process : 65nm, 45nm, 32nm, 22nm
  4. 4. Roadmap of Intel Microarchitecture :
  5. 5. Roadmap of Intel Microarchitecture • "Tick-Tock" is a model adopted by chip manufacturer Intel Corporation since 2007 to follow every microarchitectural change with a die shrink of the process technology. • Every "tick" is a shrinking of process technology of the previous microarchitecture • Every "tock" is a new microarchitecture. • Every year, there is expected to be one tick or tock.
  6. 6. Architectural change Fabrication process Microarchitecture Codename Release date Processors Marketing names Tick Die shrink 65 nm P6, NetBurst Presler, Cedar Mill, Yonah January 5, 2006  Core  Pentium 4  Pentium D  Pentium M  Pentium Dual- Core  Celeron Tock New microarchitecture Core Conroe July 27, 2006[2]  Core 2  Pentium Dual- Core  Pentium  Celeron Dual- Core  Celeron  Celeron M Tick Die shrink 45 nm Penryn November 11, 2007[3] Tock New microarchitecture Nehalem Nehalem November 17, 2008[4]  Core i3  Core i5  Core i7  Pentium  Celeron  Xeon Tick Die shrink 32 nm Westmere January 4, 2010[5][6] Tock New microarchitecture Sandy Bridge Sandy Bridge January 9, 2011[7] Tick Die shrink 22 nm Ivy Bridge April 29, 2012 Tock New microarchitecture Haswell Haswell June 2nd 2013
  7. 7. The Core Microarchitecture • Example Processors : Core 2 Duo • First Released : July 27, 2006 • designed from ground up, but is similar to the Pentium M microarchitecture in design philosophy. • The power consumption of these new processors is extremely low • new technology included in the design is Macro-Ops Fusion, which combines two x86 instructions into a single micro- operation • This architecture is a dual core design with linked L1 cache and shared L2 cache • No Hyperthreading
  8. 8. Nehalem Microarchitecture • Used in Core i3, i5, i7 Processors(1st Generation) • released : November 17, 2008 • Some Features : – An important change is the enlargement of the L2-cache by 50% compared with Merom processors. This means a L2-cache of 3 respectively 6 megabytes. Since this increases the amount of data available for quick processing by the CPU, it is probably the most important advantage of the Penryn architecture for most users and mainly responsible for the measured performance improvement. – Hyperthreading reintroduced – reduction in L2 cache size, as well as an enlarged L3 cache that is shared by all cores. – Intel QuickPath Interconnect in high-end models replacing the legacy front side bus – Integration of PCI Express and DMI into the processor in mid-range models, replacing the northbridge – Integrated memory controller supporting two or three memory channels of DDR3 SDRAM or four FB-DIMM2 channels • Improvements over Core : – 10-25% more single-threaded performance / 20-100% more multithreaded performance at the same power level – 30% lower power usage for the same performance – Nehalem provides a 15–20% clock-for-clock increase in performance per core(average)
  9. 9. Sandy Bridge Microarchitecture • Used in Core i3, i5, i7 Processors(Second Generation) • released : January 9, 2011 • Upgraded features from Nehalem include: – 32 kB data + 32 kB instruction L1 cache and 256 kB L2 cache per core – Shared L3 cache includes the processor graphics (LGA 1155) – 64-byte cache line size – Decoded micro-operation cache and enlarged, optimized branch predictor – Improved performance for transcendental mathematics, AES encryption (AES instruction set), and SHA-1 hashing – Advanced Vector Extensions (AVX) 256-bit instruction set with wider vectors, new extensible syntax and rich functionality – Intel Quick Sync Video, hardware support for video encoding and decoding – Up to 8 physical cores or 16 logical cores through Hyper-threading – Integration of the GMCH (integrated graphics and memory controller) and processor into a single die inside the processor package. In contrast, Sandy Bridge's predecessor, Clarkdale, has two separate dies (one for GMCH, one for processor) within the processor package. This further integration reduces memory latency even more. • Developed primarily by the Israel branch of Intel, the codename was originally "Gesher" (meaning "bridge" in Hebrew). The name was changed to avoid being associated with the defunct Gesher political party
  10. 10. Ivy Bridge Microarchitecture • Used in Core i3, i5, i7 Processors(Third Generation) • released : April 29, 2012 • Features : – The Ivy Bridge CPU microarchitecture is a shrink from Sandy Bridge and remains largely unchanged. – die shrinking improvement(tick) – 22nm manufacturing process – backward compatible with Sandy Bridge – Trigate Transistors (3D Transistors)
  11. 11. Ivy Bridge Microarchitecture (Continued) • Trigate Transistors(3D Transistors) : – allowing for essentially three times the surface area forelectrons to travel. – reduce leakage and consume far less power than current transistors. – This allows up to 37% higher speed, or a power consumption at under 50% of the previous type of transistors used by Intel – faster switching speed
  12. 12. Haswell Microarchitecture • Currently Under Development • Will be Used in Core i3, i5, i7 Processors(Fourth Generation) • Will be released on June 4, 2013 • Micoarchitecutre Improvement over “Ivy Bridge”
  13. 13. • Next we will discuss some of Intel Brand Names currently in the market such as : – Core 2 Duo – Core i Series(i3, i5, i7) – Intel Atom
  14. 14. Core 2 Duo • Core Microarchitecture family (codename penryn) • 2 cores on single die • 45nm Technology • An important change introduced is the enlargement of the L2-cache by 50% compared with previous processors. This means a L2-cache of 3 respectively 6 megabytes. Since this increases the amount of data available for quick processing by the CPU, it is probably the most important advantage of the Penryn architecture for most users and mainly responsible for the measured performance improvement.
  15. 15. Core i series • Core i3, i5, i7 • Nehalem or Sandy Bridge Microarchitecture Based • Different types of new Intel processors brands to suit various user needs. – Core i3 : This processor is considered to be the low end, budget processor – Core i5 processor : This is considered the mid-range and mainstream – Core i7 processors :are considered high end Processors
  16. 16. Core i Series star rating : • Their relative levels of processing power are also signified by their Intel Processor Star Ratings, which are based on a collection of criteria involving their number of cores, clockspeed (in GHz), size of cache, as well as some new Intel technologies like Turbo Boost and Hyper- Threading. • Core i3s are rated with three stars, i5s have four stars, and i7s have five.
  17. 17. Core i series Comparison between i3, i5, i7 • We will compare i3, i5, i7 according to : – Number of Cores – Cache Sizes – Hyper Threading – Intel Turbo Boost Technology
  18. 18. Core i series Comparison between i3, i5, i7 • Number of Cores : – Core i3 : all of them are 2 cores – Core i5 : either 2 cores or 4 cores – Core i7 : All of them are 4 cores • Cache Size : – Core i3 : All of them have 3 MB Cache – Core i5 : All of them have 6 MB Cache(Except for some) – Core i7 : All of them have 8 MB Cache
  19. 19. Core i series Comparison between i3, i5, i7 Hyper-Threading • Intel has introduced a technology called Hyper-Threading. This enables a single core to serve multiple threads. • The main function of hyper-threading is to decrease the number of dependent instructions on the pipeline. • Hyper-threading works by duplicating certain sections of the processor—those that store the architectural state—but not duplicating the main execution resources. This allows a hyper-threading processor to appear as the usual "physical" processor and an extra "logical" processor to the host operating system • core i3, i5 , and i7 all of them have hyper threading • The number of threads is double the number of cores : – Core i3 : 2 Cores  4 Threads – Core i5 : • Either 2 Cores That support Hyper Threading  4 Threads • or 4 Cores( True 4 Cores models don’t support Hyper Threading)  The Total number of Threads is 4 too – Core i7 : 4 cores  8 Threads
  20. 20. Core i series Comparison between i3, i5, i7 Intel Turbo Boost Technlogy • The Intel Turbo Boost Technology allows a processor to dynamically increase its clockspeed whenever the need arises. The maximum amount that Turbo Boost can raise clockspeed at any given time is dependent on the number of active cores, the estimated current consumption, the estimated power consumption, and the processor temperature. • none of the Core i3 CPUs have Turbo Boost • All Core i5 and Core i7 are equipped with Turbo Boost Technology
  21. 21. Intel Atom • ultra-low-voltage IA-32 and Intel 64 (x86-64) CPUs • originally designed in 45 nm CMOS with subsequent models, codenamed Cedar, using a 32 nm process • Atom is mainly used in netbooks, nettops, embedded applications ranging from health care to advanced robotics, and mobile Internet devices (MIDs). • All Atom processors implement the x86 (IA-32) instruction set • Atom processors are based on the Bonnell microarchitecture • Bonnell Microarcitecture : is a CPU microarchitecture used by Intel Atom processors which can execute up to two instructions per cycle • Feature 16 pipleline stages • The Bonnell microarchitecture represents a partial revival of the principles used in earlier Intel designs such as P5 and the i486, with the sole purpose of enhancing the performance per watt ratio

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