1. Verification for System Companies
Value Proposition
hagai@veriest-v.com
www.veriest-v.com
Hagai Arbel, CEO
February 2015

2. Table of Content
• What is verification and how it fits in System development flow
• How they do it in the ASIC world and why is it interesting
• Fundamentals of functional verification
• Value proposition through case studies
• About Veriest

3. Simplified Hardware development flow
System
Architecture
FPGA design Board
Development
Software
Development
Design Document
VHDL coding
Simulations
Initial LAB Integration
Bug-fix
System integration and
QA
Bug-fix
System Shipment
Bugs at
Customer’s

4. Pain 1 – No sufficient FPGA documentation
System
Architecture
FPGA design Board
Development
Software
Development
Design Document
VHDL coding
Simulations
Initial LAB Integration
Bug-fix
System integration
and QA
Bug-fix
System Shipment
Bugs at
Customer’
s
• Only that specific designer
know what he did
• No sufficient review there will
be no architecture and system
bugs

5. Pain 2 – Long Initial LAB integration
System
Architecture
FPGA design Board
Development
Software
Development
Design Document
VHDL coding
Simulations
Initial LAB Integration
Bug-fix
System integration
and QA
Bug-fix
System Shipment
Bugs at
Customer’
s
• The FPGA designer is
simulating – No 2nd set of eyes
• VHDL simulation is limited –
Finding only the basic and
simple bugs
• LAB integration is long
– Hard to find bugs in the
LAB
– Hard to know whether
there is a board or FPGA
logic problem

6. Pain 3 – Long QA cycle
System
Architecture
FPGA design Board
Development
Software
Development
Design Document
VHDL coding
Simulations
Initial LAB Integration
Bug-fix
System integration
and QA
Bug-fix
System Shipment
Bugs at
Customer’
s
• Many FPGA logic bugs still
exist in the code
• Debug cycle is long
• Waiting the time of FPGA
designers, Software engineers
and System engineers

7. Pain 4 – System Shipment with FPGA bugs still in the code!
System
Architecture
FPGA design Board
Development
Software
Development
Design Document
VHDL coding
Simulations
Initial LAB Integration
Bug-fix
System integration
and QA
Bug-fix
System Shipment
Bugs at
Customer’
s
• Although QA cycle is long,
FPGA bugs may still exist
• These bugs may be visible only
when Software is updated
• Recall of equipment, lost of
market
• Debug is extremely hard

8. The answer is functional verification
FPGA design
Design Document
VHDL coding
Very basic VHDL simulation
‘Modern’
Design Functional
Verification
Bug Fix

9. It is done similarly in ASIC companies
LAB debug becomes
hard
FPGA technology
booms – 100s of MHz
and Millions of LUTs
Complex systems –
more faults at
customer’s
FPGA
Development
NEEDS
Verification

10. Verification principles
• Defining verification goal – coverage plan and test plan.
• Using an object-oriented programming language to implement the
verification environment.
•
• Verification tools are complete platform for a verification project
management, control and implementation.
• In practice:
– Engineer or team that is expert in that
– System Verilog language, UVM methodology and Verification shelf packages
(VIPs)

11. ‘Modern’ Verification for FPGA – Taking some principles from ASIC
• Use the tools and methodologies from ASIC world but:
– Can stop at 90%, not 100% because we have the LAB
– Adopt to lower level of documentation
– Single verification engineer ‘serves’ 3-5 FPGA designer (unlike ASICs, which is 1:1
verification / designers)

12. Verification cost
• FPGA team grows by 20-30%
• New discipline – Need to recruit a team or to get help from expert verification companies
• Need to invest a bit more in documentation – Verification engineer must know what he is
checking

13. Verification benefits
• The months spent in verification are saved during debug cycle – FPGA gets to the LAB
clean
• Verification is not specific software oriented – The FPGA will work according to its
specification even when software is changed
• Less chance for bugs at customer’s site
• Much better time to market – Entire system debug cycle is much shorter

14. In the last 5 years system companies are ramping up their capabilities
• Using consulting firms such as Veriest and
• Ramping their own internal teams

15. Bench mark – Framer verification (1 FPGA designer)
Design LAB
bringup
QA Total TTM
(months)
No Verification 2 3 3 8
With Verification 3 1.5 1.5 6
Designer Verification QA Total
Man months
No Verification 8 NA 3 11
With Verification 4.5 4.5 1.5 10.5
Time To Market
Effort

16. Bench mark – Ethernet processing FPGA (5 FPGA designers)
Design LAB
bringup
QA Total TTM
(months)
No Verification 6 5 5 16
With Verification 6 2 2 12
Designer Verification QA Total
Man months
No Verification 59 NA 15 74
With Verification 41 14 6 61
Time To Market
Effort

17. Bench mark – Video processing FPGA (10 FPGA designers)
Design LAB
bringup
QA Total TTM
(months)
No Verification 8 8 5 21
With Verification 10 3 2 15
Designer Verification QA Total
Man months
No Verification 170 NA 42 212
With Verification 124 35 18 177
Time To Market
Effort

18. About Veriest
• Founded: 2007 in Tel Aviv
• Headquarter: Tel Aviv, Israel
• Offices: Israel: Management and R&D
Serbia: R&D
• Professional Services:
ASIC and FPGA design, verification and software
Exceptional expertise in Verification