Fixed point computing element design for transcendental functions and primary operations in speech processing

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Fixed-Point Computing Element Design for
Transcendental Functions and Primary Operations in
Speech Processing
Abstract:
This brief presents a fixed-point architecture based on a reconfigurable scheme for integrating
several commonly used mathematical operations of speech signal processing. The proposed
design can perform two transcendental mathematical operations called logarithm and powering,
and three commonly used computations with similar operations named polynomial calculation,
filtering, and windowing. By analyzing the adopted algorithms of the above five operations, a
simplified computing unit is designed. This unit can combine six types of operations by
reconfiguring the data paths, and the same multiply– add architecture can be reused for reducing
the redundant usage of logic gates. The experimental results reveal that the proposed design can
work at a 200-MHz clock rate, and its gate count only has 11.9k. Compared with the results of
the floating-point function, the median errors of the proposed design for computing the powering
and logarithmic functions are 0.57% and 0.11%, respectively. Such results indicate that this
simple architecture can be effectively used in most speech processing applications. The proposed
architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.
Enhancement of the project:
Existing System:
With respect to the related studies, Ramamoorthy et al. first noticed the suitable priorities of the
Newton–Raphson method (NRM) for computing the square-root operations. In this brief, a
finding was discovered that the division in the recursion of the NRM could be removed, when
the target function of the NRM changed to the inverse square root. Seth and Gan also presented a
hardware design based on the NRM. In this design, several lookup tables (LUTs) and polynomial

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expansions (PEs) are used to approximate the value of the inverse square root, for reducing the
number of multiplications and additions. However, the memory requirement for the LUTs and
the PEs was still a drawback. Auger et al. developed a multiplier free algorithm based on a
dichotomous coordinate descent (DCD) technique for the solutions of division, square root, and
logarithmic operations. The DCD-based algorithm included only additions, shift operations, and
logic conditions. Such an algorithm was very proper to design a relevant low-gate-count
architecture. Nam et al. developed a 3-D graphics rendering engine for a handheld system. The
design, respectively, used two LUTs for computing the reciprocal square root and the power
function. It might hugely increase the chip area. To solve this problem, Kim et al. proposed an
arithmetic architecture that can compute the most fixed-point transcendental functions using the
equivalent logarithmic functions. To reduce the usage of memory, the fractional part of the
logarithmic functions was approximated by an LUT with several adders and shift operations.
This brief provided a fast and area-efficient solution for various transcendental functions for a
fixed-point 3-D graphic application. However, the designed LUTs limited the range of the output
value, so it was hard to be used for other applications
Disadvantages:
 Gate count is high
 Power consumption
Proposed System:
Computation Analysis for Designing FSM
In the proposed design, the basic operations of the abovementioned algorithms are first analyzed.
We note that the required basic operations in the above algorithms are very similar. That is, the
designed hardware can use the same architecture to compute these operations, so the required
hardware area can be reduced. Table I lists the analyzed operations for calculating the operation
that is listed. The first and second columns list the function type and its included computation,
respectively. The rest of the columns show the necessary operations for these types of
computation.

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TABLE I NECESSARY BASIC OPERATIONS FOR THE COMPUTATION
Fig. 1 totally consists of seven states, in which six states are used to compute different kinds of
computations, as listed in Table I. These states include:
1) idle (IDLE);
2) BLA phase one (BLA P1);
3) BLA phase two (BLA P2);
4) the NRM for computing the power function (NRM);
5) EBS;
6) polynomial computation/ convolution (POL/CON);
7) windowing (WIN).
Notably, each state implies several behaviors, and the different behaviors are decided by the
values of the corresponding counter and state register.

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Fig. 1. Example of state diagram for computing (a) logarithmic function (Mode = 0) and (b) power function (Mode
= 1). Dashed lines: controller will not go in these states with the different mode.
Fig. 2 shows the architecture of the proposed system, including a 4-to-2 multiplexer, a 16-word
dual-port SRAM, a parallelin-serial-out (PISO) register, a mathematical computing unit, and a
corresponding controller. As shown in Fig. 3, the input Mode determines which operation is
performed by the proposed system when the Act signal rises up. Then, the input Order means the
order of polynomial, a filter, or a window function. The dual-port SRAM has 16-word space and
32-bit word length, which can temporally store the coefficients. In addition, the PISO register
determines the behavior for the calculation of the EBS state. Finally, the multiplexer array can
decide which coefficients need to be stored in the SRAM, or to be computed.
Fig. 2. Architecture of the proposed system.

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Fig. 3 represents the architecture of the proposed mathematical computing unit. This architecture
includes only a multiplier, an adder, a barrel shifter, a comparator, two registers, and seven
multiplexers. In this design, the same arithmetic logics can be reused for different kinds of
computations, as listed in Table IV. As shown in Fig. 3, the left multiplexer selects the
coefficients for different kinds of computations. The middle multiplier, adder, and shifter can
reorganize the computing flow to achieve distinct functionalities.
Fig. 3. Architecture of a mathematical computing unit.
1) The following content briefly describes how the proposed hardware works with these six
states. 1) IDLE: This state keeps waiting until the signal Act rises up, and then, the input
Mode decides the next states for computing the corresponding function.
2) BLA P1: This state responses for computing BLA P1. The signal Sig_C is sent from the
comparator in the mathematical computing unit, and is used to conform whether the next
state is BLA P1 or BLA P2.
3) BLA P2: This state is used to compute the second phase of the BLA. The computation of
the second phase will be kept until the Count value reaches M. Afterward, the next state
is decided by the value that is saved in the stage register. If the value is one, the system
will go back to BLA P1 to calculate the value of log2(B). Otherwise, the next state will be
set to the NRM for computing (log2(B))−1
.

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4) NRM: This state executes the iterations of Newton’s method for computing the power
function. Cnt records the computation cycle. The value of xk
2M
will be first computed by
the EBS when PCount is zero.
5) EBS: This state is to compute εI , εF , and xk
2M
. In each cycle, the PISO shifts a bit to the
controller for determining the behavior of the EBS.
6) POL and WIN: These two states response for the computation of the polynomial and the
convolution, respectively.
Advantages:
 Improve the reusable efficiency.
 Gate count is reduced
 Power reduced
Software implementation:
 Modelsim
 Xilinx ISE

Fixed point computing element design for transcendental functions and primary operations in speech processing

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Fixed point computing element design for transcendental functions and primary operations in speech processing