Current Status of Solar PV Technologies, Manufacturing Issues and Research Trends

Current Status of Solar Photovoltaic
Technology Platforms, Manufacturing
Issues and Research
Steve Hegedus
Institute of Energy Conversion
University of Delaware
With assistance from IEC staff:
Brian McCandless (CdTe), Bill Shafarman (CIGS)

Photonic Spectra Webinar “PV manufacturing and research” Hegedus 09/27/12 #1

Outline
 Introduction to IEC at U of Delaware
 PV trends, growth in scale, contribution to energy production
 Crystalline Si PV status, baseline technology, near term focus:
 New methods emitter formation, passivation and device
architecture

 Thin Film PV status, baseline technology and near term focus:
 Cu(InGa)Se2 : wide gap alloys, improved 2-step selenization
 CdTe: higher deposition T , substrate
 a-Si/nc-Si (briefly) : multijunction, collapse of the a-Si industry

 Two common PV myths

Institute of Energy Conversion at U of Delaware
 Founded in 1972 to perform thin-film PV research
 World’s oldest continuously operating
solar research facility
 First 10% efficient thin film solar cell (1980)
 Dept of Energy University Center of Excellence
for Photovoltaic Research and Education (1992) First flexible
 Soft funded - government and industry contracts 10% cell
 2012 staff: 11 professional, 3 tech, 2 admin, 5 post
doc, >20 grad students (4 depts)
4x4 inch
 Recently rec’d $8.4M from DOE (3 year grants) minimodule


IEC Research Program Goals
 Expand the fundamental science and engineering base for
thin film and c-Si photovoltaics to improve performance

 Transfer these technologies to large-scale manufacturing
 IEC has been responsible for growth of several PV start-ups
through technology transfer and validation

 Provide workforce with PV scientists and engineers
 >40 graduates since 1992 (PV Center of Excellence)


IEC Technology Thrust Areas
 Thin film polycrystalline CuInGaSe2-based (CIGS) solar cells
 Thin film polycrystalline CdTe solar cells
 Silicon-based solar cells
 Front and back contact heterojunction (a-Si/c-Si)
 Thin film tandem a-Si and nc-Si


IEC Facilities: complete capability for fabrication and
characterization of thin film and c-Si solar cells
 Over 20 thin-film deposition systems: PECVD (vhf/rf/dc), HWCVD,
PVD, Vapor Transport, sputtering, H2S/H2Se reaction, chemical bath
 Materials characterization: XRD, GIXRD, VASE, EDS, SEM, AFM,
AAS, XPS, FTIR, Raman, optical trans+refl, Hall effect
 Device fabrication: complete capability for high efficiency solar cells:
c-Si (front heterojunction and IBC), CdTe, Cu(InGa)Se2 , a-Si
 Laser and mechanical scribing for monolithic module fabrication
 Device characterization: J-V, J-V-T, QE, C-V, OBIC, accelerated life
stress (damp-heat, ambient, light)

The Big Picture:
PV applications and achievements


PV can be installed anywhere, 10’s Watts to 100’s Megawatts


Recent worldwide achievements
 Installation: 17 GW in 2010 (100% growth), 30 GW in 2011 (70% growth)
 Average annual growth >50% p/y for decade
 EU: PV providing 2-4% of annual electricity in Spain, Germany, Italy
 May 2012 Germany received >10% from PV
 On one day >40% (22 Gigawatts peak supply out of 27 GW installed)
 US: 5.7 GW installed, 2 GW in CA
 Over 70% of 2011 installations are ‘utility scale’ or > 100 kW
 Worlds largest PV power plant 250 MW Aqua Caliente Project (CA, thin film)
 Creating hundreds of thousands of jobs
 400,000 in Germany; 100,000 in US
 R&D, manufacturing, supply chain (materials), system design, installation


Trend in PV applications: 1990-2009
 1995: PV demand driven by off-grid applications
 After 1995: Innovative policy in Japan, Germany stimulated market
for grid-connected residential and commercial
 >2008: Asian Si modules drove down prices, increased installations

 >2010: Significant growth in
utility scale > 1 MW projects

 2012: First year of flat or
 negative growth in decades,
projected to recover 2013


Industry in turmoil: ‘roller coaster ride’
 Significant consolidation, bankruptcy, closures in past 2 years
 Top companies for years suddenly quit PV or bankrupt
 Worldwide capacity ~ twice demand yet demand still growing
 Huge excess inventory
 Shrinking profits - many companies selling at loss to compete
 c-Si done much better in price and efficiency than many expected,
squeezing thin film start ups
 Renewed emphasis on improving performance since costs so low


Brief Overview of PV Basics


What is a PV device?
Direct converter of light into electricity:
photons in, electrical current (DC) out

Three critical processes:
Light Absorption + Carrier Generation + Carrier Collection
(current flow) (deliver P to load)
e- V+
e-
h+ load
h+ V-
charge separation


Cell efficiencies vs. bandgap EG
 Record performance single junction cells vs. theoretical limit
 Expect maximum
performance
with EG ≈ 1.5 eV
 But theor eff >25%
possible EG ≈ 1 – 1.8 eV
a-Si/nc-Si 2J
 Many thin film, III-V options


Commercial Scale PV Devices
 Single crystal or multicrystalline Si wafers
 Dominate market: 85-90% of sales
 Solar grade Si, lower qual than IC
 Module efficiency: 14-20%
 Low cost Asian Si driving prices down

 Thin films (1-3 µm polycrystalline or amor)
 Ultimately lower cost than Silicon wafers (??)
 On glass, metal or plastic foils
 Diverse materials, techniques
 Lower quality, imperfect crystallization, more defects
 Module efficiency: 8-14%
 Unique advantages in building integrated products
 10-15% of market, #2 PV company is TF CdTe (First Solar)


One common PV challenge: reducing gap
between champion cell and module efficiency
Multi c-Si
and TF CIGS
both ~20%
cell efficiency.
But mc-Si
has more
mature module
technology.

Wolden et al, JVST-A 29 (2011) 030801

Why efficiency matters – fixed BOS costs
Levelized cost of Energy:
• Lifecycle costs/energy
• LCOE costs include
Balance of System which
scale with # modules, area
• Lower eff = higher BOS$
• More rack, wiring, install $
• y-intercept is system price
without module
• Si modules ‘selling’ at $0.9/W
Or $120/m2
Wang et al Renewable and Sustainable Energy Rev (2011)


Crystalline Si (c-Si) Technology
and Advanced Concepts


Standard commercial Si PV cell process
start

900°C
900°C

400°C finish

Commercial Si Solar Cell, Eff ~ 15-17%

Front contact (Screen printed Ag fired through SiN)

Random
textured
F and R
(~ 0.3 µm)


World record Si solar cell: PERL
• PERL cell: Passivated Emitter, Rear contact Locally diffused
• 2-step emitter (thin n between contact and thick n+ under contact)
• UNSW, AU, 1998; very complex design, not manufacturable

Cell Voc (V) Isc (mA/cm2) FF(%) Eff(%)
PERL 0.70 42 81 24.7

Conflicting emitter properties: pn junction vs
resistance vs absorbing ‘dead layer’
property Advantage Disadvantage
Increase thickness •Reduce lateral R for •Increase absorption in
current flow to Ag highly defect layer
contact (photons not converted
•Prevent melting Ag SP to e-h pair), lower blue
metal penetrate to base QE and Jsc
Increase doping •Reduce lateral R •Increase defects and
•Reduce contact R with recombination (Io) so
Ag or other metal grid decrease Voc

Increase bandgap •Decrease absorp loss •Increase lateral
•Increase band bending, resistance significantly,
reduce recomb (Io) req second conductive
layer ($$)

Why not ‘tune’ the emitter to have properties it
needs only where it needs them?
 Why not a 2 step emitter – spatially specific?
 different thickness and doping where needed?
 acknowledge that current flow is 2D not 1D

 Why not replace with wider bandgap material?
 Why not get rid of the emitter all together*

* On the front of the device


Industrially proven high efficiency Si
solar cell concepts
 Three commercial proven enhancements (full size wafer
results)
 PERL/SE: passivated+selective emitter, rear localized contact
 HIT: ‘HJ intrinsic thin’ a-Si/c-Si heterojunction
 IBC: ‘interdigitated back contact’ rear emitter and base contact


Hi Eff concept #1: the 2-step ‘selective emitter’
Conventional 1 step 2 step emitter: thinner n+ everywhere
thick emitter except under metal n++

Increased blue Applied
response with Materials
thinner n+ website


SE option 1: laser doping + plating metal

http://www.photonics.com/Article.aspx?AID=40098


SE option 2: deposit
thicker n++ then etch
back

• requires alignment of front metal
to thicker n++ mesa


Thinner vs selective emitter: Voc, Isc, FF, Eff

Gauthier “Industrial Approaches of Selective Emitter on Multicrystalline Silicon Solar Cells”
24th Eu-PVSEC (2009) 2-CV.5.46


Hi Eff #2 Heterojunction Solar Cell: deposited a-Si
passivation layers reduce surface recombination
10nm (p)a-Si:H 10nm (i)a-Si:H
30nm (n)a-Si:H

Rear
 Device: n-type c-Si wafer and 5-10 nm
60nm
ITO Contact PECVD a-Si layers (EG=1.7-1.8 eV)
(Al)
hυ (i) a-Si:H surface passivation layers (both sides)
(p)a-Si:H emitter (front)
Front
Contacts
(n)a-Si:H back contact (rear)
(Ag)
300μm n-c-Si wafer All a-Si and contacts deposited <200°C (low $,
Electron Current less defects, no warping thin wafers)
 High efficiency and VOC (Sanyo/Panasonic):
EF EC
η = 23% champion cells, 19% modules
VOC = 740mV
EV
Hole Current

Two modes of c-Si Surface Passivation by a-Si:H
Field effect passivation:
Defect neutralization by H atoms: Increased band bending at junction
Reduce c-Si surface dangling bonds Repel/separate majority or minority carrier
Reduce recombination (IO), increase VOC Reduce Io, increase VOC
EC
EC

EF EF
EG,c-Si EG,a-Si:H EG,a-Si:H
EG,c-Si
EV
EV
c-Si Substrate a-Si:H film (n)c-Si Substrate (i)a-Si:H film
PECVD a-Si:H provides best passivation and processing < 300 °C, high VOC
Si surface cleaning critical to good passivation
Well-established, slow deposition rate, easily control thickness ~ 5-10 nm


Hi Eff Si #3: Interdigited back contact (IBC) cell


Standard front junction vs all back contact


IBC spectral response higher in
short (blue) and long (IR) wavelengths


Sunpower IBC: highest efficiency module


Integration of both device concepts: SHJ-IBC Cell
TCO
p-type a-Si
intrinsic a-Si

n-type c-Si
intrinsic a-Si
n-type a-Si
TCO
Silicon heterojunction (SHJ) solar cell. Interdigitated back contact (IBC) solar cell.

First published •intrinsic a-Si buffer
results on SHJ-IBC •separate a-Si p
By IEC (APL 2007) and n regions
IBC-SHJ solar cell (IEC structure)


IEC Multichamber PECVD for HIT and IBC-SHJ

4 chambers plus 2 load lock, DC/RF/VHF plasma
Multiple substrate sizes (1x1 up to 12x12 inch)

Thin Film PV
 Common Features
 Monolithic Integration via laser patterning: enabling
technology
 Lower efficiency: TF PV best suited for BIPV, large power
plants

 Status and Critical Issues
 Cu(InGa)Se2
 CdTe
 A-Si/nc-Si (briefly)


Monolithic Series Interconnection : laser scribe
 Allows structuring of large area uniform thin film layers into series
connected junction diodes; critical technology for TF PV
 Three laser scribing steps (patterning steps P1, P2, P3)
 P1) bottom conductor; P2) semiconductor junction; P3) top conductor

 Width of cells determines module current (ISC), # in series determines VOC

Chapter 12, Handbook of Photovoltaic Science and Eng (Luque, Hegedus), Wiley 2011

TFPV applications: BIPV
 Appearance preferred for building-integrated PV
Semitransparent a-Si
Architectural skylight

85kW Shell Solar
Cu(InGa)Se2 in Wales


Flexible a-Si on SS: BIPV (flex laminate)
 Flexible PV for roll-out rooftop installation (USSC triple
junction/SS)


4 MW of CdTe installed by Tucson Electric


15 MW of 3Sun Tandem Thin Si in
Altomonte, Calabria Italy


Cu(InGa)Se2
Thin Film Solar Cells

Help from
Bill Shafarman


Why thin film CuInSe2 alloys for PV?
 Direct bandgap chalcopyrite materials with high absorption coefficient
 Extraordinary compositional tolerance
 Alloy with Ga, Al, Ag, S to engineer bandgap  improve performance,
TF tandem
 Can be deposited on glass or light flexible substrates: polymer, foils
 Highest device and module efficiency of any TF PV technology
 Multiple deposition technologies with promise of scalability
 Attracted considerable private investor funding
 Outdoor module stability demonstrated


Cu(InGa)Se2 Thin Film PV
 Performance
 Highest cell efficiency = 20.3% (ZSW 2010)
 Efficiency ≥ 18% from several laboratories
 Sub-module eff. = 17.8% with
area > 800 cm2 (Solar Frontier 2012)
 12–14% module efficiency from
companies worldwide Grid
ZnO:Al
 Manufacturing CdS
 Many companies with various approaches
Cu(InGa)Se2
1. Reaction of metal precursors (2-step)
 Low cost deposition of metals Mo
 Batch process: “selenization”
Substrate
2. Multi-source evaporation (1-step)
 In-line process, high temp


Cu(InGa)Se2 Optical Absorption
 High optical absorption of sunlight
 Direct bandgap
 Complete absorption in ~ 1 µm thickness (CdTe very similar)
 Reduces requirements for minority carrier transport
1
bsorption

0.8
CIGS
0.6
Si
elative A

0.4

0.2
R

0
0.001 0.01 0.1 1 10 100 1000
thickness (µm)


Cu(InGa)Se2 Grain Structure
 Films are polycrystalline with rough surface
 Grain size ~ 0.1 – 1 µm depends on deposition conditions
 e.g. substrate temperature during evaporation
 But device performance is remarkably insensitive to grain size,
morphology

Cu(InGa)Se2

1µm
Mo
deposited at 400°C deposited at 550°C
Wilson, Birkmire, Shafarman Proc. 33rd IEEE PVSC (2008)


CuInSe2 Alloys with wider EG: Al, Ga, S
 CuInSe2 has EG=1.0 eV, limits eff., major focus 20 yrs is to raise EG
 Wide range of ternary, quaternary alloy options
 Recent focus on alloys with Ga/(Ga+In), S/(S+Se), Ag/(Ag+Cu)

 Alloying changes EG also lattice constants (no epi!), band alignment

x = alloy
fraction:
Al/(In+Al)
Ga/(In+Ga)
Ga/(In+Ga)
S/(Se+S) a x=0
b x=0.24
c x=0.61


Increasing efficiency and VOC at higher EG
Increasing EG with alloy (Ga, Ag, S) Failure to capture benefit of larger EG
to push efficiency at EG >1.3 eV due to VOC/ EG<1 is critical issue

Contreras et al, 37th IEEEE PVSC, Seattle 2011

Process 1: Elemental Co-evaporation
 Simultaneous delivery of elemental vapors
to hot substrate
 Makes higher efficiency devices than 2-step
 Independent control of each element
 Ga/(In+Ga) gradient
 bandgap gradient

Substrate Heater
Substrate at 400-600°C
Film Growth Monitor
To vacuum pump
Thermal Evaporation Pbase ≈ 1x10-6 Torr
Sources for Cu, In, Ga, Se, (S) Prun ≈ 2x10-5 Torr


IEC Cu(InGa)(SeS)2 Co-evaporation
 Five source system for Cu-In-Ga-Se-S
 Boron nitride Knudsen cells
 Typical temperatures
T(Cu) = 1350°C
T(In) = 1000°C
T(Ga) = 1100°C
T(Se) = 300°C
 Source design and
T control are
critical features


Process 2: 2-step Precursor Reaction
 Advantages: lower cost, higher uniformity + materials utilization
 Many precursor deposition options with Cu, In, Ga –
 sputtering – commercially available
 electrodeposition – high utilization, non-vacuum, batch
 ink printing – high utilization, non-vacuum, continuous
Reaction Mo/Cu(InGa)Se2
Mo/Cu/Ga/In H2Se/H2S
or Se/S

400 - 600°C
 Reaction in hydride gases (H2Se, H2S) or elemental vapors (Se,S)
 Multi-step reaction pathway to form Cu(InGa)Se2


Cu(InGa)Se2 Precursor Reaction
 IEC H2Se / H2S reactor
 reaction in quartz tube of glass/Mo/Cu-In-Ga precursor layers
 atmospheric pressure with flowing H2Se / H2S / Ar / O2
 Temperature-time cycle critical to uniformity, manufacturibility


CIGS Module Process Flow

Clean Mo dc P1 laser CIGS
Substrate sputtering scribe deposition

ZnO:Al P2 mech. HR ZnO CdS bath
deposition scribe deposition deposition

P3 mech. Attach EVA/glass Module
Scribe buss bars lamination completion


CIGS thin film manufacturing status: > 30MW real capacity
Manu- Deposition Champion Current Deposition Deposition Process comments
facturer Technology product % nameplate Process Con´s
apa capacty MW/a Pro´s

Manz 1-stage co- 15.1 30 Simpler, more Sacrifices efficiency Glass-glass
(Würth) evaporation 120 advanced process Cd- buffer
Solibro 14.4
Global Solar 3-stage co- 15 (cell) Highest known TF Complex process SS substrate.
Energy evaporation 13 (mod) module efficiency glass/polymer

MiaSolé Reactive sputter 15.7 >40? good efficiency Complex process SS substrate, cut +
potential, rel. stitch, glass-glass
small capex exp. CdS-dry

Solar 2-step: Sputter+ SF: 17.8 980 advanced Sacrifices efficiency glass-glass
Frontier, H2Se/S- SF: 14.1 process, Higher OpEx than CdS
Stion/ Selenization (manu) 5 + 135 potentially higher evap. glass-glass
TSMC Stion: 14.5 +300 CapEx Cd-free
TSMC 15.1

Avancis, 2-step: 30 + 100 Glass-glass
Hyundai Sputter+Se- +100 CdS (Cd-free)
evap.+ RTP-
cryst./H2S
Solo Power 2-step 15.1% cell 30 + 400 Good metal Sacrifices efficiency SS substrate
electroplate- 13.5% mod utilization, rel. low Polymer
Selenization CapEx CdS
Source: MarkusSpectra/ Webinar San Francisco‚ Feb. 2012 plus adds from09/27/12 #55
Photonic Beck Photon “PV manufacturing and research” Hegedus the author

Two Current research issues: Cu(InGa)Se2
 Fundamental understanding of relation between wide EG
alloys and device performance with multisource evaporation

 Control uniformity and reduce process time with Se/S reaction


1. New wide gap alloy (AgCu)(InGa)Se2
 Ag addition to Cu(InGa)Se2 lowers melting temperature, better surface
mobility, potential for improved structural hence electronic quality

 Ag increases bandgap by up to 0.25 eV,

 Single phase over entire range of Ag–Cu and Ga–In alloying


Notable wide EG cell results with (AgCu)
 Cells: SLG/Mo/(AgCu)(InGa)Se2/CdS/ZnO/ITO/grid/MgF2
 High Eff = 17.6% with Eg ≈ 1.3 eV High VOC = 890 mV with Eg ≈ 1.6 eV

Hanket, et al., Proc. 34th IEEE PVSC

2. H2Se/H2S reaction of Cu-Ga-In Precursors:
Ga segregation at rear limits EG and Voc
• 30’ H2Se@450°C, 15’ H2S@450°C • 15’ H2Se@450°C, 15’ H2S@450°C
• Complete H2Se reaction prior to H2S • Partial H2Se reaction prior to H2S
• Ga segregated at back, none at front • Ga uniform, higher at front
• Low EG at front junction, low Voc • Higher EG at front junction, higher Voc
60 60

50 Se 50
)

)
com osition (%

Se

positio (%
40 40

n
30 Cu Mo 30
Cu
Mo
20 In
p

20
In

com
10 10
S Ga S Ga
0 0
0 20 40 60 80 0 20 40 60 80
sputter time (min) sputter time (min)
Hankett et al, Proc 4th World PVSEC, 2006


Single step H2Se process vs. Three-step H2Se/H2S process
20
Single step process Eff Voc Jsc FF
Temp,

2
Single-step : 8.3% 0.383 V 37.0 mA/cm 58.7%
°C

450 2
3-step : 14.2% 0.599 V 32.2 mA/cm 73.5%
Single step: 0

J (mA/cm )
H2Se

2
20 60 ~ 90 Time, min Mo
Three-step process -20 Ga accumulation
550
Temp,

Mo
°C

400 -40 Ga homogenization
1st step : 2nd step : 3rd step :
H2Se Ar H2S
-0.2 0.0 0.2 0.4 0.6 0.8
20 50 10 10 20 10 V (V)
Time, min
Process optimization  Ga distributed uniformly with 3 step H2Se/H2S
 Major improvement in VOC and Eff.

CdTe Thin Film Solar Cells

Help from
Brian McCandless


Why CdTe TF solar cells?
 Chemically stable, simple phase diagram, easy surface passivation
 Film deposition by a variety of scalable techniques
 Optimized cells require post-dep halide (Cl) exposure at ~ 400C
 Easily adapted to monolithic integration
 Low cost: thin absorber, low cap ex equipment costs, high dep rate
 Best laboratory cell efficiency >17%, best module 14% (First Solar)
 Presently lowest price PV available (First Solar)
• First Solar <$0.75/W manufacturing cost
• 2-3 hours from glass to module with 13% efficiency
• Responsible for US lead in module manufacturing
• Thin film success story!


Superstrate CdTe/CdS cell
configuration

Glass superstrate (SLG or advanced)
SnO2 (comm or more complex TCO)
HR layer (intrinsic TCO, ~ 20 nm)
CdS (n-type, 30-50 nm)

CdTe (p-type, 2-4µm) + CdCl2 step
Contact (contains Cu as dopant)


CdTe/CdS heterojunction cell structure:
grain boundaries, S-Te interdiffusion, QE
CdS depletion
Contact CdTe1‐xSx alloy
(Cu+other) 1.0

Quantum efficiency
Bandgap shift
0.8
p-CdTe
0.6

0.4
n-CdS CdCl2 HT
0.2 as-deposited
Zn2SnO4
Cd2SnO4
glass 0
400 500 600 700 800 900
Wavelength (nm)


CdTe/CdS module processing

Clean
glass/SnO2 First Deposit Post Dep
Substrate Scribe CdS, CdTe CdCl2 Treat

CdTe Surface Second
Third Back
Etch Scribe
Scribe Contact

Tabbing,
Junct box Test
Encapsulate


CdTe deposition technology
T > 500°C T < 400°C
Atmospheric Screen
Spray
High Cl Golden Photon Print
O2 Matsushita

Vacuum Abound, USF PVD Canrom
CSS
No Cl First Solar, Calyxo
ED
BP Solar
VT PrimeStar/GE,
Low O2 NREL, IEC
XunLight 26
rf Sp


IEC CdTe Research using Vapor Transport Dep
Develop process for Eff > 15% on moving glass substrate ( 3 cm/min) to
provide basis for in-line manufacturing
Optimize: CdTe deposition, substrate, contacts, CdCl2 annealing
 Surface chemistry, interdiffusion, impurities, grain growth
Currently IEC CdTe work is proprietary; evaluating alternative glass, TCO, buffer
layers

CdTe
Vapor Transport System Source CdCl2 Reactor

CdTe film growth: TSS, thickness, rate
Substrate temp 500ºC 570ºC AFM 20 x 20 m
5 m, 8 m/min 5 m, 8 m/min

Faceted morphology, grain size increases with substrate temperature
Film thickness 550ºC 550ºC
1 m, 8 m/min 23 m, 8 m/min

Grain size increases proportional with CdTe thickness
Growth rate 550ºC 550ºC
6 m, 8 m/min 6 m, 81 m/min

Grain size inversely proportional to CdTe growth rate


Fundamental CdTe issues
 Compensating defects → doping and defect control difficult
 Difficult to achieve NA>5E14 cm3
 High hole affinity → non-ohmic back contact (needs p+ Cu2Te)
 Unable to increase Voc>0.85V which is only 60% of EG

 Highest efficiencies with non-commercial substrate
 Replace SLG with BSG glass ($) : more transparent, higher T deposition

 Replace SnO2:F (FTO) with Cd2SnO4/Zn2SnO4 (CTO/i-ZnO)
 Higher CdTe dep T allows improved grain structure (higher Voc, FF)


New substrates enable higher CdTe dep T  higher Eff
Commercial Tec10 SLG/SnO2:F/i-ZTO vs R&D GL/Cd2SnO4/i-ZTO

Record CdTe FF>81%
With new substrates

13.5%
16.5%

[McCandless et al, to be submitted (2012)]


CdTe thin film manufacturing status
Manu- Deposit Champion Current Depo Depo Process module
facturer Tech. product % apa nameplate Process Con´s
capacity MW/a Pro´s

First Solar Low Press 14.4 mod 2,700 Simple and Global player, Glass-
Vapor Champ lab cell: closing matured Quality ?? glass
17.3% process, high
Transport several lines
thruput

Primestar/ “Thermal evap.“ 12.8 mod 30, started ? Techn. Status Glass-
GE construct ? glass
400 MW, on
hold
Abound Low Press 15.7 cell Started Glass in, Lower Glass-
Solar Thermal evap. construct, module out. efficiency? glass
(CSU) Closed 2012
Calyxo Atmos. press. 13.4% 80 Potential low Quality? Glass-
(Q-cell) thermal evap. Champion lab cost, high rate Techn. Status glass
cell: 16.2% ?

Source: Schock / SNEC Shanghai‚ May 2012 plus adds from Dimmler 38th IEEE PVSC

Brief discussion of a-Si based multijunction PV

Steven Hegedus


Why amorphous Si (a-Si:H) for thin film PV?
 Unique among thin film PV technologies
 Easily vary doping (p or n), bandgap, crystallinity (a-nc), thickness,
 Well-established commercially viable multijunction process (>20 yrs)

 Minimal deposition steps: PECVD plus sputter back contact (<200°C)
 Highest cell efficiency (3-junction a-Si/a-SiGe/nc-Si) : 14% (stabilized)
 Commercial module stabilized efficiency (2J a-Si/nc-Si) : 9-10%
 Least difference between best cell and typical module efficiency:
Oerlikon, Sharp, AMAT have tandem 12% cell and 10% module
 Challenge: native and light induced defects low mobility+lifetime 
limit efficiency; even as lowest cost PV in market, cannot compete


Multijunction multibandgap a-Si solar cells
‘micromorph’
a-Si/nc-Si tandem
optimum trade-off
between cost and
efficiency

Eff=6-7% Eff=9-11% Eff=12-13-% Eff=12-13%
Chapter 12, Handbook of Photovoltaic Science and Eng (Luque, Hegedus), Wiley 2011


Current a-Si PV commercial status: deathwatch
 ~ 10-15 companies bought Oerlikon or AMAT turn-key fab lines 2007-
2009 during Si feedstock shortage and PV price increase
 Low efficiency, high cap ex, new a-Si PV at disadvantage
 Most now closed (bankrupt), few operating in Asia
 Subsequent c-Si overcapacity and PV module price collapse squeezed a-
Si from the cost side (its strength) now multi-Si comparable cost
 Appl Matl closed their a-Si fab line 2010, Oerlikon Solar closed 2012

 United Solar (USSC/ECD) flex roofing product: closed 2012 after 30
yr
 Sharp (?), Panasonic, Kaneka, NexPower, Astraenergy-Chint; 3Sun
(Italian JV Sharp-Enel) are leading players, ~9-10% efficient 2J
 58 MW Sharp micromorph tandem installed in CA in 2012


Dispell Two PV Myths


I heard it takes more energy to make a solar
module than they can ever produce?
 NO!!!!
 How many years of operation before reach energy break-even point?
 Energy payback is <1.5 years for today’s crystalline Si wafer modules,
even less for next generation thin film modules
 With 25 year warrantees, today’s PV modules will be net producers of
clean, CO2-free electricity for at least 23 years!


I heard you would have to cover the country
with solar modules to make any ‘real’ energy?

Total energy:
200x200 miles
(50% coverage)

Electricity only:
100x100 miles
(50% coverage)


Questions? Then buy this book!
2nd Edition (2011) of the most
comprehensive PV book
-1100 pages
-6 new chapters
-8 different cell technologies
-TCO’s
-performance characterization
-batteries, inverters, system
-policy, economics


Back-up slides


2012 TF PV industry expected production
Very fluid, obtained from Renewable Energy World on-line 6/4/2012
2102 Top Thin Film PV manufacturers

Solibro - CIGS 20
3Sun - thin Si 30

T-Solar - thin Si 35
Miasole - CIGS 40

Trony - thin Si 80
NexPower - thin Si 90
Astroenergy - thin Si 120
Sharp - thin Si 180
Solar Frontier - CIGS 620
First Solar - CdTe 1530
0 200 400 600 800 1000 1200 1400 1600
2012 MW produced


Double vs Triple Junction: United Solar/ECD

Guha, SPIE Photovoltaics 2009

Cadmium toxicity: perception problem
 Widely studied by Brookhaven Natl Lab and NREL
 Cd: lung, kidney, bone carcinogen
 CdTe: less soluble, more stable, less toxic
 Cd is by-product of Zn mining
 Choices: react Cd with Te and encapsulate behind glass in controlled
environment and generate clean energy; or leave it in exposed ore
tailings
 Not released to environment during roof-top residential fire
 EU: granted CdTe PV an exemption; politically vulnerable
 US: CdTe PV not classified as toxic waste (EPA)
 Japan, Korea: banned CdTe PV and closed research
 First Solar recycling/insurance program, “behind the fence”
 www.nrel.gov/cdte

Current Status of Solar PV Technologies, Manufacturing Issues and Research Trends

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