1. Independent Study Project Report – EECE4993:
Digitally Tunable Lowpass-Notch Filter Design forAnalog
Front-Ends in Brain Signal MeasurementApplications
Kaidi Du
Dept. of Electrical and Computer Engineering
Northeastern University, Boston, USA
In Support of College Honors in Electrical Engineering
Advisor:
Prof. Marvin Onabajo
8/26/2015

2. 1
Table of Contents
Abstract........................................................................................................................................................2
I. Introduction.........................................................................................................................................2
II. Tunable Filter Design .....................................................................................................................3
a. Fifth Order Elliptic Low-pass Notch Filter ..................................................................................3
b. Digital Notch Frequency Tuning Methodology............................................................................4
c. Binary Digital Tuning Approach...................................................................................................6
III. Simulation Results ..........................................................................................................................8
IV. Measurements ...............................................................................................................................14
V. Future Work — Automatic Digitally-Assisted Calibration ..........................................................22
VI. Conclusion .....................................................................................................................................24
References..................................................................................................................................................25

3. 2
Abstract
A digitally tunable Transconductance-Capacitor Low-pass Notch Filter (LPNF) for
Electroencephalography (EEG) application is presented in this research report. Since EEG signals
fall into four basic frequency bands, δ (1-4Hz), θ (4-8Hz), α (8-13Hz), and β (13-40Hz), but the
power line interference at 60Hz, created by electrode cable and circuitry, has much higher power
than the brain signals, the power line interference negatively affects the accuracy of the EEG
system. Therefore, a combination of a notch filter and a high-order low-pass filter are employed
in this work. With the development of microcontrollers, digitally controlling methods are
becoming more frequent in integrated circuit (IC) implementations. Hence, a digital tuning method
for this LPNF is in high demand. Due to the digital tuning approach, an automatic calibration of
this Gm-C LPNF through a microcontroller can be realized in the future.
Keywords—Digital Tuning Method; Binary Way; Lowpass-Notch Filter; Operational
Transconductance Amplifier.
I. Introduction
Electroencephalography (EEG) systems monitor activities in the brain by recording electrical
signals from cerebral nerve cells along on the scalp. As the only non-invasive method for
measuring brain activities from human scalps, it plays an important role in effectively diagnosing
patients with severe neuron muscular disorders, and therefore, it is widely used in research of brain
nerves and clinical applications [1]. EEG signals can be categorized into four basic bands, δ (1-
4Hz), θ (4-8Hz), α (8-13Hz), and β (13-40Hz) [2]. Since brain signals are very weak, ranging from
2 to 200μV, compared to one strongest noise source from the power line, it is beneficial to include
a Lowpass-Notch filter (LPNF) in the analog front-end (AFE) of EEG measurement devices [3].
However, fabrications and environmental variations may cause the actual notch frequency to
deviate from the nominal value, so there must be a reliable tuning method for the LPNF
architecture so that the notch frequency can be easily calibrated.
As a microcontroller has advantages of small size, programmable input and output peripherals,
all-in-one design (containing the processor, RAM, and I/O), and low cost, it can be used to test
preliminary designs prior to integrating analog signal processing and digital calibration circuits on
the same chip, for which the work described in this report is preparing for.
The LPNF used in this work was mainly referenced by a single-ended Gm-C filter structure
reported in [2] and a fully-differential CMOS LPNF designed by Kainan Wang [3] from the
Analog and Mixed-Signal Integrated Circuit Research Laboratory at Northeastern University. In
Section II, a digitally tunable notch filter will be elaborated on. Then, a comprehensive simulation
assessment with Cadence software tools and actual measurements will be presented in Section III
and Section IV. The focus in Section V is on the future improvements of this digitally tunable
LPNF. Conclusions are given in Section VI.

4. 3
II. Tunable Filter Design
a. Fifth Order Elliptic Low-pass Notch Filter
The Transconductance-C (OTA-C) filter in Fig. 1 realizes a fifth-order elliptic filter with a
low pass transfer function that contains a notch. The null frequencies play an important role in
determining the notch frequency and stopband ripple in the lowpass filter. Because the brain
signals of interest only fall into low frequencies ranging up to 40Hz, the signals out of this range
will be treated as noise. In order to remove these noises, it is necessary to have a lowpass filter
with extremely narrow transition band. Not only does this kind of elliptic filter act as a lowpass
filter, but also it is used as a notch filter. Since the strong power line interference of the EEG
system is around 60Hz, it is required to have sufficient attenuation at the notch frequency. In this
fifth-order elliptic filter the null frequencies are very close to the cut-off frequency of the transfer
function, which is why the notch is just at the outside of the passband range. Hence, this fifth-order
elliptic filter can combine the advantages of both notch filters and lowpass filters.
The schematic of the active LPNF is shown in Fig. 1. Since this LPNF is mainly designed for
on-chip circuits, the size (chip area) of the filter is one of the main concerns. As OTAs in integrated
circuits are much smaller than that of the on-chip inductors, the OTA-C filter is a better design
choice for implementation on chips. Additionally, it allows designing the passband gain of the
active filters by using Gm-C structures. In this design, all six OTAs have the same transconductance
Gm, so the pass band gain is 0dB. Moreover, in order to have deeper notch, two null frequencies
of the OTA-C filters are combined to a single notch in this fifth-order elliptic filter. According to
the schematic in Fig. 1, these two null frequencies can be expressed as:
𝑓1 =
1
2𝜋
𝐺 𝑚𝑂𝑇𝐴
√𝐶𝐿1 𝐶2
(1)
and
Fig. 1. Schematic of the fifth-order single-ended low-pass notch filter [2].

5. 4
𝑓2 =
1
2𝜋
𝐺 𝑚𝑂𝑇𝐴
√𝐶𝐿2 𝐶4
(2)
and
𝑓1 = 𝑓2 (3)
Consequently, the notch in this design has deeper notch compared to the standard elliptic filter. As
tuning for GmOTA may affect the ripples in the pass-band specification, it is better to fix the value
of Gm during the tuning process. Therefore, the only way to tune the notch frequency is changing
the values of CL1 and CL2 or C2 and C4 by using variable capacitors or by adding extra capacitors
with switches. Usually, the switch is easier to be operated when one of its two terminals is
grounded. Fig. 1 shows that one terminal of CL1 and CL2 is grounded but C2 and C4 are floating
between two nodes, so adding extra capacitors with switches to CL1 and CL2 is a better way to tune
the notch frequency than using C2 and C4.
b. Digital Notch Frequency Tuning Methodology
Since microcontrollers can read, implement, and generate digital signals at I/O interfaces,
which are chip-operable, inexpensive, and programmable devices with nice peripherals, low power
consumptions, and good cross-platform supports; they are widely used in the electronics field [5].
The LPNF in this paper is intended for an on-chip application, and therefore, a tuning method
involving digital controlling by microcontrollers or on-chip digital circuits will help to compensate
for manufacturing process variations. According to the equation (1) and (2), tuning the grounded
capacitors, which are CL1 and CL2 shown in Fig. 1, will lead to the changes of the notch frequency.
Hence, if the value of the grounded capacitors can be controlled by digital signals, digitally tuning
the notch frequency will be put into practice. In other words, the notch frequency of the LPNF can
be digitally controlled by connecting digital switches in series with extra capacitors which are
parallel with the fixed-value grounded capacitors (CL1 and CL2). The detailed schematic is
presented in Fig. 2. In the circuit, all switches are implemented with discrete N-type metal-oxide-
semiconductor (NMOS) transistors. Each NMOS switch controls the connection of one extra
grounded capacitor. The drain of the NMOS connects to one lead of an extra grounded capacitor
and its source terminal connects to the ground. In the future, the gate voltage of the NMOS can be
controlled by a programmable microcontroller. Currently, the on and off state of the NMOS switch
was manually controlled by connecting the gate either to the low voltage power line (3-4V) or to
ground, which imitated the digital output signal of the microcontroller. If the voltage at the gate is
higher than the threshold voltage of the NMOS, which is equal to voltage value of the low voltage
power line, the extra capacitor will be connected parallel with the fixed value grounded capacitors
so that the total value of the grounded capacitors increases and the notch frequency decreases.
Digitally tuning of the notch frequency is possible by controlling the on and off states of the NMOS
switches.

6. 5
Fig. 2. Actual LPNF circuit connection.

7. 6
c. Binary Digital Tuning Approach
For the purpose of tuning the notch frequency of the LPNF with the largest tuning range and
the smallest increment, it will be effective and economic to use a binary-weighted method for
changing the total values of grounded capacitors. There are 8 bits available in the LPNF design of
this work. The value of capacitor at each bit is calculated based on the binary arithmetic rules:
𝑐𝑎𝑝𝑐𝑖𝑡𝑜𝑟 𝑣𝑎𝑙𝑢𝑒 𝑎𝑡 𝑡ℎ𝑒 𝑛 𝑡ℎ 𝑏𝑖𝑡 ≅ 𝑐𝑎𝑝𝑎𝑐𝑖𝑡𝑜𝑟 𝑣𝑎𝑙𝑢𝑒 𝑎𝑡 𝐿𝑆𝐵 × 2 𝑛
(4)
The calculated capacitor value for each code is shown in Table 1.
Table 1.Calculated extra grounded capacitor value at each code.
nth Binary Code Capacitor Value at Each Code
0 (LSB) 0.33 µ𝐹
1 0.66 µ𝐹
2 1.32 µ𝐹
3 2.64 µ𝐹
4 5.28 µ𝐹
5 10.56 µ𝐹
6 21.12 µ𝐹
7 (MSB) 42.24 µ𝐹
The sum of all extra capacitors 84.15 µ𝐹
In order to actually build this filter, the component selections also depend on the availability
of standard values offered by component distributors. To make calculations simple, all GmOTA
values of OTAs are set to be 9.6mS; C1, C3, and C5 are equal to 30µF; C2 and C4 are equal to 20
µF (Fig. 2). Cancelling out the power interference at 60Hz is the main goal of this LPNF, so the
notch frequency 60Hz. If all values are substituted into equations (1)-(3), the desired notch
frequency would be achieved:
𝑓𝑖 = 60 =
1
2𝜋
9.6 × 10−3
√ 𝐶𝑔𝑟𝑜𝑢𝑛𝑑_𝑡𝑜𝑡𝑎𝑙_𝑖 × 20 × 10−6
(5),
where 𝑓𝑖 = 𝑓1 = 𝑓2 = 𝑛𝑜𝑡𝑐ℎ 𝑓𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 and 𝐶𝑔𝑟𝑜𝑢𝑛𝑑_𝑡𝑜𝑡𝑎𝑙_𝑖 = 𝐶𝐿𝑖 + ∑ 𝐶𝑙𝑖_𝐷𝑛𝑛 , 𝑖 = {1,2}, 𝑛 =
{0,1,2,3,4,5,6,7}
After rearranging equation (4), it results in 𝐶𝑔𝑟𝑜𝑢𝑛𝑑_𝑡𝑜𝑡𝑎𝑙_𝑖 ≅ 32.42 µ𝐹 = 𝐶𝐿𝑖 + ∑ 𝐶𝑙𝑖_𝐷𝑛𝑛 . To
determine the acceptable range of CLi, the worst case must be considered. According to the data
sheets, all capacitors have the same 20% tolerance and the range of the GmOTA is from 6.7 × 10−3
𝑆
to 13 × 10−3
𝑆. Therefore, there are two extreme cases:
a. If GmOTA is at the lower bound (i.e., GmOTA=6.7 × 10−3
𝑆) and all capacitors are at the upper
bound (i.e., 𝐶 × (1 + 20%), when only 𝐶𝐿𝑖is used), the notch frequency, which is at the
upper bound of the notch frequency range, must be greater than 60Hz. The mathematical
inequality expression is

8. 7
60 <
1
2𝜋
6.7 × 10−3
√𝐶𝐿𝑖_𝑛𝑜𝑚𝑖𝑛𝑎𝑙 × (1 + 20%) × 20 ∗ (1 + 20%) × 10−6
(6),
implying that:
𝐶𝐿𝑖_𝑛𝑜𝑚𝑖𝑛𝑎𝑙 < 10.96µ𝐹 (7)
b. If GmOTA is at the lower bound (i.e. GmOTA=13.0 × 10−3
𝑆), and all capacitors are at the
upper bound (i.e. 𝐶 × (1 − 20%), when all extra capacitors are used), the notch frequency,
which is at the lower bound of the notch frequency range, must be less than 60Hz. The
mathematical inequality expression is
60 >
1
2𝜋
13.0 × 10−3
√(𝐶𝐿𝑖 + 𝐶 𝑋 𝑆𝑢𝑚
) × (1 − 20%) × 20 ∗ (1 − 20%) × 10−6
(8),
where the sum of the nominal value of all extra capacitors is CX_Sum, implying that:
𝐶𝐿𝑖 + 𝐶 𝑋_𝑆𝑢𝑚 > 92.90µ𝐹 (9)
The larger 𝐶𝐿𝑖 is, the smaller 𝐶 𝑋_𝑆𝑢𝑚 is. Because it is better to design with a small increment,
𝐶 𝑋_𝑆𝑢𝑚 should be small. In this prototype, the largest 𝐶𝐿𝑖 value is 10 µ𝐹, requiring that 𝐶 𝑋_𝑆𝑢𝑚
must be greater than 82.92 µ𝐹. Hence, the capacitor value at the LSB must be 𝐶𝐿𝑆𝐵 >
82.92µ𝐹
28−1
≅
0.325µ𝐹. The closest available capacitor value of 0.33 µ𝐹 was selected, and therefore, the closest
available capacitors at other bits are summarized in Table 2. The expected results for the typical
and two worst cases are listed in Table 3.
Table 2. Available extra grounded capacitor value at each code.
nth Binary Code Typical Value
Anticipated
minimum value with
variation
Anticipated
maximum value
with variation
0 (LSB) 0.33 µ𝐹 0.26 µ𝐹 0.40 µ𝐹
1 0.68 µ𝐹 0.54 µ𝐹 0.82 µ𝐹
2 1.2 µ𝐹 0.96 µ𝐹 1.44 µ𝐹
3 2.7 µ𝐹 2.16 µ𝐹 3.24 µ𝐹
4 5.6 µ𝐹 4.48 µ𝐹 6.72 µ𝐹
5 12 µ𝐹 9.60 µ𝐹 14.40 µ𝐹
6 22 µ𝐹 17.60 µ𝐹 26.40 µ𝐹
7 (MSB) 47 µ𝐹 37.60 µ𝐹 56.40 µ𝐹
The sum of all extra
capacitors (𝐶 𝑋_𝑆𝑢𝑚)
91.51 µ𝐹 73.21 µ𝐹 109.81 µ𝐹

9. 8
Table 3. Expected notch frequency results in different situations.
Case gm fmin fmax
Typical Case 9600 µ𝑆 33.90954426 Hz 108.0379579 Hz
Worst Case 1 (G_min, C_max) 6700 µ𝑆 19.72169675 Hz 62.83457623 Hz
Worst Case 2 (G_max, C_min) 13000 µ𝑆 57.39896815 Hz 182.8767517 Hz
III. Simulation Results
All circuits were designed and simulated with ideal components in Cadence. The schematic in
Fig. 3 and Fig. 4 shows the macro model of the LPNF in Cadence. The OTA is modeled as shown
in Fig. 5. Table 4 summarizes the simulated specifications of the standalone LPNF. The results are
indicated in Table 5. The screenshots of the Cadence simulations are shown in Fig. 6, Fig. 7, and
Fig. 8. Fig. 6 represents the simulation result when all capacitors and OTAs are at the nominal
values. When the ideal switch codes are 11111111 (all NMOS switches are on), the simulated
notch frequency is at 34.51Hz; when ideal switches codes are 01000110, the notch frequency is at
60.20Hz; when ideal switches codes are 00000000 (all NMOS switches are off), the notch
frequency is at 111.68Hz. Table 5 shows the simulation results in other two extreme cases (the
largest gm with smallest capacitors and the smallest gm with largest capacitors, which corresponds
to Fig. 7 and Fig. 8).
Fig. 3. Macro Model layout design of LPNF in Cadence.

10. 9
Fig. 4. Zoomed-in macro model for OTA.
Fig. 5. OTA macro model.

11. 10
Table 4. Parameters for simulations in Cadence.
Parameters in Cadence Simulation
Typical GminCmax GmaxCmin
Code when Notch
@60Hz
01000110 00000110 11101101
Voltage to Open the
Switch
< 999.9mV < 999.9mV < 999.9mV
Voltage to Close the
Switch
> 1V > 1V > 1V
R_OpenSwitch 192KΩ 192KΩ 192KΩ
R_ClosedSwitch 365.2mΩ 365.2mΩ 365.2mΩ
CL_1 10μF 12μF 8μF
CL_2 10μF 12μF 8μF
cl2_D7 47μF 56.4μF 37.6μF
cl2_D6 22μF 26.4μF 17.6μF
cl2_D5 12μF 14.4μF 9.6μF
cl2_D4 5.6μF 6.72μF 4.48μF
cl2_D3 2.7μF 3.24μF 2.16μF
cl2_D2 1.2μF 1.44μF 0.96μF
cl2_D1 0.68μF 0.82μF 0.54μF
cl2_D0 0.33μF 0.4μF 0.26μF
D27 0 0 1
D26 1 0 1
D25 0 0 1
D24 0 0 0
D23 0 0 1
D22 1 1 1
D21 1 1 0
D20 0 0 1
cl1_D7 47μF 56.4μF 37.6μF
cl1_D6 22μF 26.4μF 17.6μF
cl1_D5 12μF 14.4μF 9.6μF
cl1_D4 5.6μF 6.72μF 4.48μF
cl1_D3 2.7μF 3.24μF 2.16μF
cl1_D2 1.2μF 1.44μF 0.96μF
cl1_D1 0.68μF 0.82μF 0.54μF
cl1_D0 0.33μF 0.4μF 0.26μF
D17 0 0 1
D16 1 0 1
D15 0 0 1
D14 0 0 0

12. 11
Typical GminCmax GmaxCmin
D13 0 0 1
D12 1 1 1
D11 1 1 0
D10 0 0 1
c1 30μF 36μF 24μF
c2 20μF 24μF 16μF
c3 30μF 36μF 24μF
c4 20μF 24μF 16μF
c5 30μF 36μF 24μF
Gm 9600μS 6700μS 13000μS
Rin 26KΩ 26KΩ 26KΩ
Rout 1MΩ 1MΩ 1MΩ
Vsin 1mV 1mV 1mV
Table 5. Summary of simulation results.
G_typ and C_typ G_min and C_max G_max and C_min
The closest frequency to 60Hz 59.98 Hz 59.70 Hz 60.25 Hz
fmin 34.51 Hz 20.14 Hz 58.34 Hz
fmax 111.17 Hz 65.16 Hz 187.93 Hz
Gain @60 Hz -61.64 dB -58.78 dB -66.79 dB
Gain @fmin(11111111) -64.77 dB -62.64 dB -66.83 dB
Gain @fmax(00000000) -60.83 dB -59.28 dB -62.55 dB
Switch Code to place the notch
at 60HZ (MSB→LSB)
01000110 00000110 11101101

13. 12
Fig. 6. Simulated transfer function with typical values of Gm and for capacitors.

14. 13
Fig. 7. Simulated transfer function with minimum Gm and maximum capacitor values.

15. 14
Fig. 8. Simulated transfer function with maximum Gm and minimum capacitor values.
According to the simulation results in Table 5, it is clear that if gm is fixed, the notch frequency
is inversely correlated to the value of the grounded capacitors (CL1 and CL2). On the other hand, if
the value of the grounded capacitors is fixed, the notch frequency increases with the value of Gm.
This simulation results agree with the calculated results based on the equations (1) and (2).
IV. Measurements
The proposed filter was assembled on a breadboard with components ordered from Mouser
Electronics. Table 6 lists the values of key components parameters shown in Fig. 2. The photo of
the circuit is displayed in Fig. 9. All OTAs are biased identically and operate with the same supply
voltages of ±18V. There are some differences between Table 6 and Table 4. All ideal switches in
Fig. 2 are replaced by NMOS switches with the same threshold voltage. The values of CL_1 and
CL_2 in measurements are larger than those in simulations. The reason is that manufacturing
variations were higher than the expected. After adding extra capacitors to CL_1 and CL_2, the
total value of the fixed grounded capacitors was 40μF to place the notch frequency at 60Hz. More
specifically, 30μF capacitors were added to the original CL_1 (10μF) and CL_1 (10μF), which are

16. 15
marked as four 15μF capacitors in Fig. 9. As a result, the smallest frequency which the notch can
reach is about 58Hz.
Table 6. Parameters during measurements based on the schematic in Fig. 2.
Measurement
Notch Frequency(Hz) 60 Hz(Typical) 58 Hz 120 Hz
Code 11111100 11111111 00000000
D27 1 1 0
D26 1 1 0
D25 1 1 0
D24 1 1 0
D23 1 1 0
D22 1 1 0
D21 0 1 0
D20 0 1 0
D17 1 1 0
D16 1 1 0
D15 1 1 0
D14 1 1 0
D13 1 1 0
D12 1 1 0
D11 0 1 0
D10 0 1 0
NMOS Threshold 1V
VDC 3.75V
R_buffer1 10KΩ
R_buffer2 62KΩ
C_buffer 0.001μF
CL_1 40μF
CL_2 40μF
cl2_D7 47μF
cl2_D6 22μF
cl2_D5 12μF
cl2_D4 5.6μF
cl2_D3 2.7μF
cl2_D2 1.2μF
cl2_D1 0.68μF
cl2_D0 0.33μF
cl1_D7 47μF

17. 16
Notch Frequency(Hz) 60 Hz(Typical) 58 Hz 120 Hz
Code 11111100 11111111 00000000
cl1_D6 22μF
cl1_D5 12μF
cl1_D4 5.6μF
cl1_D3 2.7μF
cl1_D2 1.2μF
cl1_D1 0.68μF
cl1_D0 0.33μF
c1 30μF
c2 20μF
c3 30μF
c4 20μF
c5 30μF
vsin 1mV

18. 17
Fig. 9. Photo of the LPNF.

19. 18
Fig. 10 shows the measured transfer function of the LPNF in Fig. 9. This transfer function is
based on the collected data from measuring output voltage and input voltage at different
frequencies with a Tektronix DPO2024B oscilloscope. It shows that the range of notch frequency
in the measurements is from 58Hz to 120Hz depending on the digital code setting. The captured
signals at points 1, 2 and 3 in Fig. 10 are shown in Figures 11-16 (point 1, 2, and 3 are all for the
transfer function with the code for a notch at 60Hz). In Figures 11-16, the unit of the vertical axis
is dBV(RMS) and the unit of the horizontal axis is Hz. Fig. 11 and Fig. 12 show that when the
input signal is at point 1 (5Hz) in Fig. 10, the output signal has approximately the same amplitude
as the input signal. In other words, the gain at 5Hz is almost 0dB as expected. Fig. 13 and Fig. 14
show that the gain at point 2 (55 Hz) in Fig. 10, where stop-band attenuation occurs, is about -
70.3-(-30.3)=-40dB. Fig. 15 and Fig. 16 show that when the input signal is at point 3 (60Hz) in
Fig. 10, where the notch frequency is located, the gain is -98.1-(-28.8)=-69.7dB. The flat line in
Fig. 16 indicates that the output signal is below the noise level, which agrees with expectations.

20. 19
Fig. 10. Transfer function of the LPNF circuit.

21. 20
Fig. 11. Input signal waveform and FFT at point 1.
Fig. 12. Output signal waveform and FFT at point 1.
Fig. 13. Input signal waveform and FFT at point 2.

22. 21
Fig. 14. Output signal waveform and FFT at point 2.
Fig. 15. Input signal waveform and FFT at point 3.
Fig. 16. Output signal waveform and FFT at point 3.

23. 22
V. Future Work — Automatic Digitally-Assisted Calibration
In the future, microcontrollers can be added to control this LPNF design. The microcontrollers
will not only control on and off states of NMOS switches, but also automatically determine which
switches are on. In other words, microcontrollers will realize the automatic calibration of the
LPNF. In order to achieve this goal, there must be a feedback circuit returning the information at
the output of the LPNF to the microcontroller. In this case, the Beagle Bone Black microcontroller
board will be used as an example. The LPNF design in this paper needs sixteen digital output pins
for controlling on and off states of the NMOS switches and two input pins for connecting the
feedback circuit. The Beagle Bone Black microcontroller board has sixty five available digital I/Os
[6]. The output “high” voltage of each digital output is 3.3V, which is higher than the threshold
voltage (1-2V) of the NMOS used in this measurement.
The major part of the feedback circuit design is the Amplitude Detector. In each cycle of the
calibration, the output of the LPNF will be monitored by the Amplitude Detector and then send
the result to the microcontroller. The logic structure of the envisioned amplitude detection scheme
is shown in Fig. 17. There are two outputs in this Amplitude Detector—the Amplitude Detector
Output and the On Detector Output. These two outputs will connect with the input pins of the
microcontroller. When the calibration of the LPNF starts, a 60Hz test signal will enter the filter,
and then the output signal of the LPNF will be compared with the reference voltages (VREF_TYP
and VREF_ON) in the Amplitude Detector. VREF_TYP is the threshold voltage for detecting that the
signal at 60Hz is cancelled out. If the amplitude of the output signal from LPNF is smaller than
VREF_TYP but larger than VREF_ON, it means that the signal at 60Hz is filtered. Similarly, VREF_ON is
the threshold voltage for detecting that the LPNF is on. When the amplitude of the output signal
from LPNF is smaller than VREF_ON, the LPNF is off. For instance, in Fig. 17, there are three sample
output waveforms from the LPNF: Waveform 1 occurs when the LPNF is powered off, so there
will be the signal which is smaller than VREF_ON coming into the Amplitude Detector; Waveform
2 happens when the notch frequency of the LPNF is at 60Hz, the amplitude of the output signal
from the LPNF will be smaller than the unfiltered typical signal amplitude VREF_TYP, which means
that most of the output signals of LPNF at 60Hz are canceled out; Waveform 3 happens when the
notch frequency of the LPNF is not at 60Hz so the amplitude of the output signal from the LPNF
is larger than VREF_TYP. To sum up, the Amplitude Detector’s output results of each waveform are
listed in Table 7.

24. 23
Fig. 17. Amplitude detection scheme in the feedback circuit for the LPNF [7].
Table 7. Output code for different waveforms.
Waveform
Amplitude Detector
Output
On Detector Output Meaning
1 0 0 LPNF is Power Off
2 1 1
Notch Frequency
Calibrated
3 0 1
Notch Frequency is not at
60Hz
The microcontroller will start calibrations with switch codes from 00000000 to 11111111,
which means that the notch frequency begins at the maximum value and gradually decreases to
the minimum value. To realize this function, the microcontroller will increase one LSB of the
switches code each time; i.e., sequentially closing switches to increase the total grounded
capacitors value with an increment of 0.33µ𝐹. When the feedback signal from the amplitude
detector is “11,” the notch frequency of the LPNF is at 60Hz and the microcontroller will stop
increasing the switches code; i.e., closing NMOS switches. Consequently, the automatically
digitally-assisted calibration through microcontrollers will be realized with the feedback circuit in
the future.

25. 24
VI. Conclusion
A digitally tunable fifth order Transconductance-Capacitor (Gm-C) Low-pass Notch Filter for
EEG applications has been presented. The main goal of this design is to realize digitally tuning of
the notch frequency to be at 60Hz so that it can filter out the power line interference signal of the
EEG front-end system. In the simulations, this LPNF achieves a 61.64dB deep notch at 60 Hz
with typical values for each component (using macro models). The notch frequency can be tuned
from 34.51 Hz to 111.17Hz. Comparatively, in the real measurement, the LPNF achieves a 69.7dB
deep notch at 60Hz. The notch frequency of the real LPNF can be tuned from 58Hz to 120Hz
through changing the total value of the grounded capacitors. Because the transconductance of the
OTA may vary due to manufacturing process variations or changes of its temperature, a difference
between simulations and actual measurements is normal. In the actual LPNF, the total value of the
grounded capacitors can be controlled by the on and off state of the NMOS switches, which
connect with extra grounded capacitors (cl1_D1~7 and cl2_D1~7 shown in Table 6) in series. By
changing the gate voltage of each NMOS switch, the connection of the extra grounded capacitors
can be easily added to the fixed grounded capacitors (CL_1 and CL_2). As the values of the extra
grounded capacitors are distributed in a binary way, changing the switches code; i.e., changing the
gate voltage, will lead to the movements of the notch frequency. The gate voltage of each NMOS
switch can be controlled by a microcontroller, such as the Beagle Bone Black microcontroller
board, and the feedback circuit will help the microcontroller to calibrate the notch frequency to be
at 60Hz. In the future, a microcontroller and a feedback circuit can be added to this LPNF design.

26. 25
References
[1] X. Li, et al., “A High Precision EEG Acquisition System Based on the CompactPCI
Platform,” in Proc. IEEE Intl. Conf. on BioMedical Engineering and Informatic (BMEI),
2014, pp. 511-516. doi: 10.1109/BMEI.2014.7002828
[2] X. Qian, Y. P. Xu, and X. Li, “A CMOS continuous-time low-pass notch filter for EEG
system,” Analog Integrated Circuits Signal Processing, vol. 44, no. 3, pp. 231-238, Sep.
2005.
[3] W. Kainan, C. Chun-hsiang, M. Onabajo, “A Fully-Differential CMOS Low-Pass Notch
Filter for Brain signals Measurement Devices with High Interference Rejection,” in Proc.
IEEE Intl. Conf. on Circuits and Systems (MWSCAS), July 2014, pp. 1041-1044. doi:
10.1109/MWSCAS.2014.6908596
[4] J. David, M. Ken, “Continuous-time Filters,” Analog Integrated Circuit Design, New York:
John Wiley & Sons, 1997, pp. 574-642.
[5] H. Kenneth, T. Daniel, “Computer, Microprocessor, and Microcontroller Architectures,”
Microcontrollers : architecture, implementation and programming, New York: McGraw-
Hill, 1992, pp. 1-40.
[6] BeagleBone, “65 possible digital I/Os,” Beagleboard.org. Available:
http://beagleboard.org/support/bone101 Mar. 2015. [Aug. 2015].
[7] L. Xu, F. Junpeng, N. Yuchi, M. Onabajo, “Test Signal Generation for the Claibration of
Analog Front-End Circuits in Biopotential Measurement Applications,” in Proc. IEEE Intl.
Conf. on Circuits and Systems (MWSCAS, Aug. 2014, pp. 949-952. doi:
10.1109/MWSCAS.2014.6908573