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Kushagra Gaur
Kushagra Gaur
EducationTechnology
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Chapter 8: Memory Management
Chapter 8: Memory Management ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Background ,[object Object],[object Object],[object Object]
Binding of Instructions and Data to Memory ,[object Object],[object Object],[object Object],Address binding of instructions and data to memory addresses can happen at three different stages
Multistep Processing of a User Program
Logical vs. Physical Address Space ,[object Object],[object Object],[object Object],[object Object]
Memory-Management Unit ( MMU ) ,[object Object],[object Object],[object Object]
Dynamic relocation using a relocation register
Dynamic Loading ,[object Object],[object Object],[object Object],[object Object]
Dynamic Linking ,[object Object],[object Object],[object Object],[object Object],[object Object]
Swapping ,[object Object],[object Object],[object Object],[object Object],[object Object]
Schematic View of Swapping
Contiguous Allocation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
A base and a limit register define a logical address space
HW address protection with base and limit registers
Contiguous Allocation (Cont.) ,[object Object],[object Object],[object Object],[object Object],OS process 5 process 8 process 2 OS process 5 process 2 OS process 5 process 2 OS process 5 process 9 process 2 process 9 process 10
Dynamic Storage-Allocation Problem ,[object Object],[object Object],[object Object],How to satisfy a request of size n from a list of free holes First-fit and best-fit better than worst-fit in terms of speed and storage utilization
Fragmentation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Paging ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Address Translation Scheme ,[object Object],[object Object],[object Object]
Address Translation Architecture
Paging Example
Paging Example
Free Frames Before allocation After allocation
Implementation of Page Table ,[object Object],[object Object],[object Object],[object Object],[object Object]
Associative Memory ,[object Object],[object Object],[object Object],[object Object],Page # Frame #
Paging Hardware With TLB
Effective Access Time ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Memory Protection ,[object Object],[object Object],[object Object],[object Object]
Valid (v) or Invalid (i) Bit In A Page Table
Page Table Structure ,[object Object],[object Object],[object Object]
Hierarchical Page Tables ,[object Object],[object Object]
Two-Level Paging Example ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],page number page offset p i p 2 d 10 10 12
Two-Level Page-Table Scheme
Address-Translation Scheme ,[object Object]
Hashed Page Tables ,[object Object],[object Object],[object Object]
Hashed Page Table
Inverted Page Table ,[object Object],[object Object],[object Object],[object Object]
Inverted Page Table Architecture
Shared Pages ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Shared Pages Example
Segmentation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
User’s View of a Program
Logical View of Segmentation 1 3 2 4 user space physical memory space 1 4 2 3
Segmentation Architecture ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Segmentation Architecture (Cont.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Segmentation Architecture (Cont.) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
Address Translation Architecture
Example of Segmentation
Sharing of Segments
Segmentation with Paging – MULTICS ,[object Object],[object Object]
MULTICS Address Translation Scheme
Segmentation with Paging – Intel 386 ,[object Object]
Intel 30386 Address Translation
Linux on Intel 80x86 ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]
End of Chapter 8

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Memory+management