1. Mahsa Ahmadi Voice: +1(857)3338452
E-mail: mahmadi@usc.edu
Canadian citizen
Los Angeles, California
Education
University of Southern California, Los Angeles, California M.Sc. in Computer Engineering 2014 – Now(GPA=3.75)
Work Experience
Physical Design Engineering Intern, Ericsson, San Jose, USA
 Work with a team of engineers involved in embedded software development for the
product line 
 Work on one or more phases of software development from design and implementation
to unit testing and system integration
 Assist senior team members in designing and writing a layer of software (in C and pearl
scripts) which will interface with various VM hypervisors
 Learn and Apply TLM (top level module) in Physical Design flow (Cadence Encounter,
Cadence EDI)
 Perl Script work
 Spreadsheet management
 14nm PD tool/flow execution(Global Foundry Libraries
Teaching Assistant, University of Southern California, Los Angeles, USA
Summer 2015
 Working as a teaching assistant for "Basic organization of Computer system" course
 Guiding students in lab sessions and through emails to help them learn the concepts Spring2014
of computer architecture such as ISA, designing controller, and data-path
TLM Lab Intern, UT
 Designed and implemented a concurrent fault discovery algorithm for a combination
gate based circuits(C++)
 Modeled RTL component by event-driven simulator( C++) Spring 2013
 Designed and implemented fault injection and fault coverage modules
 for a digital circuit (C++)
Research Assistant
 Designed and implemented an application to evaluate effects of aging on transistor (MATLAB, HSPICE) Fall 2012
 Automated aging parameter Extraction form HSPICE data of a transistor simulation using MATLAB
Selected Projects
 General Purpose Micro Processor (Cadence (Virtuoso), Perl)
 All full-custom design (schematic, layout) under Cadence (Virtuoso)
 Logic effort related path sizing, dynamic logic and clock gating implemented, power and
area optimization required
 Perl script created to read command and generate signal so to act as instruction decoder
and control unit
Spring 2015
 Designed a high performance fully customized chip that produces Fibonacci series
minimizing the area-delay product of the chip(Virtuoso)
Fall 2014
 Implemented a server/client application by sockets to simulate doctor appointment
system(C++)
Fall 2014
 Designed and implemented a 4-way set associative cache which uses LRU page
replacement policy ( Modelsim, Verilog)
Fall 2014
 Calculated Minimum Energy Point of Ultra-low Power Design in Sub-threshold Supply
Voltage (HSPIC)
Spring 2012
 Designed and implemented UART system (Verilog, Altera FPGA cyclone 4) Fall 2012
 Designed and Implemented Single Cycle, Multi Cycle, and Pipelined Processors
(Modelsim, Verilog) Spring 2011

2. Achievements
 Scholarship for Exceptional talent of UT Spring 2009
 Ranked 180 among 223,401 candidates in the nationwide university entrance Spring 2009
 Scholarship for Exceptional talent of UT Fall 2009
Skills
 Programming C/C++(skillful), MATLAB(good knowledge), Perl(good knowledge), Linux (Skillful)
 HDL Verilog(skillful), SystemC and SystemC-AMS(basic)
 Software Cadence(EDI, Encounter), Cadence(Virtuoso), Modelsim (Verilog), HSPICE, MATLAB, Microsoft
Visual C++, Openet, Wireshark, QuartesII, L-Edit, Multisim,