High-Efficiency PHEV Charger Boost Converter

A High-Performance Single-Phase AC-DC Power Factor Corrected Boost Converter for plug in
Hybrid Electric Vehicle Battery Chargers
1

Fariborz Musavi
Student Member IEEE

Wilson Eberle
Member IEEE

2

William G. Dunford
Senior Member IEEE

Delta-Q Technologies Corp.
Burnaby, BC, Canada
fmusavi@delta-q.com
Abstract -- In this paper, several conventional plug in hybrid
electric vehicle charger front end AC-DC converter topologies
are investigated and a new bridgeless interleaved PFC converter
is proposed to improve the efficiency and performance.
Experimental and simulation results of a prototype boost
converter converting universal AC input voltage to 400 V DC at
3.4 kW are given to verify the proof of concept, and analytical
work reported in this paper.
Index Terms—Bridgeless PFC, Interleaved PFC, PFC boost
converter, PHEV charger.

I.

INTRODUCTION

A plug-in hybrid electric vehicle (PHEV) is a hybrid
vehicle with a storage system that can be recharged by
connecting the vehicle plug to an external electric power
source [1]. The accepted charger power architecture includes
an AC-DC converter with power factor correction (PFC) [2]
followed by an isolated DC-DC converter with input and
output EMI filters [3], as shown in Fig. 1. Selecting the
optimal topology and evaluating power loss in the power
semiconductors are important steps in the design and
development of these battery chargers. The front-end AC-DC
converter is a key component of the charger system, and a
proper topology selection is essential to meet the regulatory
requirements of input current harmonics [4-6], output voltage
regulation and implementation of power factor correction [7].

1

The University of British Columbia
Kelowna, BC, Canada | 2 Vancouver, BC, Canada
1
wilson.eberle@ubc.ca, 2 wgd@ece.ubc.ca
II.

REVIEW OF EXISTING TOPOLOGIES

A. Conventional Boost Converter
The conventional boost topology is the most popular
topology for PFC applications. It uses a dedicated diode
bridge to rectify the AC input voltage to DC, which is then
followed by the boost section, as shown in Fig. 2. In this
topology, the output capacitor ripple current is very high [8]
and is the difference between diode current and the dc output
current. Furthermore, as the power level increases, the diode
bridge losses significantly degrade the efficiency, so dealing
with the heat dissipation in a limited area becomes
problematic. Due to these constraints, this topology is good
for a low to medium power range up to approximately 1kW.
For power levels >1kW, typically, designers parallel
semiconductors in order to deliver greater output power. The
inductor volume also becomes a problematic design issue at
high power.
LB

D1

DB

D4

Vin
D2

D3

QB

Co

L
O
A
D

Fig. 2. Conventional PFC boost converter

Fig. 1. Simplified system block diagram of a universal battery charger

In the following sub-sections, three existing continuous
conduction mode (CCM) AC-DC PFC boost converters are
evaluated, and a solution is proposed for front end AC-DC
converter.

B. Bridgeless Boost Converter
The bridgeless configuration topology avoids the need for
the rectifier input bridge yet maintains the classic boost
topology [9-16], as shown in Fig. 3. It is an attractive solution
for applications >1kW, where power density and efficiency
are important. The bridgeless boost converter solves the
problem of heat management in the input rectifier diode
bridge, but it introduces increased EMI [17, 18].
Another disadvantage of this topology is the floating input

line with respect to the PFC stage ground, which makes it
impossible to sense the input voltage without a low frequency
transformer or an optical coupler. Also in order to sense the
input current, complex circuitry is needed to sense the current
in the MOSFET and diode paths separately, since the current
path does not share the same ground during each half-line
cycle [11, 19].
Fig. 5. Proposed bridgeless interleaved (BLIL) PFC boost converter
TABLE I
REVIEW OF EXCISING TOPOLOGIES FOR BOOST CONVERTER
ConventioBridgeless
Interleaved
BLIL
Topology
nal PFC
PFC
PFC
PFC
Power Rating

< 1000 W

< 2000W

< 3000W

> 3000W

EMI / Noise
Fig. 3. Bridgeless PFC boost converter

Fair

Poor

Best

Fair

Capacitor Ripple

High

High

Low

Low

High

High

Low

Low

Magnetic Size

Large

Medium

Small

Small

Efficiency

Poor

Fair

Fair

Best

Input Main

C. Interleaved Boost Converter
The interleaved boost converter, Fig. 4, is simply two
boost converters in parallel operating 180° out of phase [2022]. The input current is the sum of the two inductor currents
ILB1 and ILB2. Because the inductors’ ripple currents are out of
phase, they tend to cancel each other and reduce the input
ripple current caused by the boost switching action. The
interleaved boost converter has the advantage of paralleled
semiconductors. Furthermore, by switching 180° out of
phase, it doubles the effective switching frequency and
introduces smaller input current ripples, so the input EMI
filters will be smaller [23-25]. It also reduces output capacitor
high frequency ripple, but it still has the problem of heat
management for the input diode bridge rectifiers.
In the following section, a new bridgeless interleaved
boost PFC converter is proposed in order to improve overall
efficiency of the AC-DC PFC converter, while maintaining
all the advantages of the existing solutions.

Fig. 4. Interleaved PFC boost converter

III.

BRIDGELESS INTERLEAVED BOOST TOPOLOGY

The bridgeless interleaved (BLIL) PFC converter shown in
Fig. 5 is proposed to address the problems discussed in
section II. This converter introduces two more MOSFETs and
two more fast diodes in place of 4 slow diodes used in the
input bridge of the interleaved boost PFC converter.
A detailed converter description and steady state operation
analysis is given in the following section. Table 1 shows the
advantages and disadvantages of each topology.

Ripple

IV.

CIRCUIT OPERATION AND STEADY STATE ANALYSIS

To analyze the circuit operation, the input line cycle has
been separated into the positive and negative half cycles as
explained in sub-sections A and B that follow. In addition,
the detailed circuit operation depends on the duty cycle,
therefore positive half cycle operation analysis is provided for
D > 0.5 in sub-section C and D < 0.5 in sub-section D.
A. Positive Half Cycle Operation
Referring to Fig. 5, during the positive half cycle, when
the AC input voltage is positive, Q1/Q2 turn on and current
flows through L1 and Q1 and continues through Q2 and then
L2, returning to the line while storing energy in L1 and L2.
When Q1/Q2 turn off, energy stored in L1 and L2 is released
as current flows through D1, through the load and returns
through the body diode of Q2 back to the input mains.
With interleaving, the same mode happens for Q3/Q4, but
with a 180 degree phase delay. The operation for this mode is
Q3/Q4 on storing energy in L3/L4 through the path L3-Q3Q4-L4 back to the input. When Q3/Q4 turn off, energy is
released through D3 to the load and returning through the
body diode of Q4 back to the input mains.
B. Negative Half Cycle Operation
Referring to Fig. 5, during the negative half cycle, when
the AC input voltage is negative, Q1/Q2 turn on and current
flows through L2 and Q2 and continues through Q1 and then
L1, returning to the line while storing energy in L2 and L1.
When Q1/Q2 turn off, energy stored in L2 and L1 is released
as current flows through D2, through the load and returns

through the body diode of Q1 back to the input mains.
With interleaving, the same mode happens for Q3/Q4, but
with a 180 degree phase delay. The operation for this mode is
Q3/Q4 on storing energy in L3/L4 through the path L4-Q4Q3-L3 back to the input.
C. Detailed Positive Half Cycle Operation and Analysis for
D > 0.5
The detailed operation of the proposed BLIL PFC
converter depends on the duty cycle. During any half cycle,
the converter duty cycle is either greater than 0.5 (when the
input voltage is smaller than half of output voltage) or smaller
than 0.5 (when the input voltage is greater than half of output
voltage).
Fig. 6 shows the three unique operating interval circuits of
the proposed converter for duty cycles greater than 0.5 during
positive half cycle operation. Waveforms of the proposed
converter during these conditions are shown in Fig. 7.

a) Interval 1: Q1 and Q2 are “ON”, and body diode of Q4 conducting

Fig. 7. BLIL PFC boost converter steady-state Waveforms at D > 0.5

b) Intervals 2 and 4: Q1, Q2, Q3 and Q4 are “ON”

Since the switching frequency of proposed converter is
much higher than the frequency of input line voltage, the
is considered constant during one switching
input voltage
period . The input voltage is given by:
(1)
√2
In a positive half cycle of the input voltage, the duty ratio
of the proposed converter determines the following voltage
relation:
(2)

c) Interval 3: Q3 and Q4 are “ON”, and body diode of Q2 conducting
Fig. 6. BLIL PFC boost converter operating at D > 0.5

The intervals of operation are explained as follows. In
addition, the ripple current components are derived, enabling
calculation of the input ripple current, which provides design
guidance to meet the required input current ripple standard.
Interval 1 [t0-t1]: At t0, Q1/ Q2 are ON, and Q3/Q4 are off,
as shown in Fig. 6-a. During this interval, the current in series

inductances L1 and L2 increases linearly and stores the
energy in these inductors. The ripple currents in Q1 and Q2
are the same as the current in series inductances L1 and L2,
where the ripple current is given by:
∆

1

(3)

The current in series inductances L3 and L4 decreases
linearly and transfers the energy to the load through D3, Co
and body diode of Q4. The ripple current in series
inductances L3 and L4 is given by:
1

∆

(4)

The input ripple current is the sum of currents in L1/L2 and
L3/L4:
1
(5)
∆
Interval 2 [t1-t2]: At t1, Q3/Q4 are turned on, while Q1/Q2
remain on, as shown I Fig. 6-b. During this interval, the
current in the four inductors each increase linearly, storing
are the same as the ripple current in series inductances L1 and
L2 as given by.
∆

∆

Similarly, the ripple currents Q3 and Q4 are the same as
the ripple current in series inductances L3 and L4:
∆

D. Detailed Positive Half Cycle Operation and Analysis for
D < 0.5
Fig. 8 shows the operating interval circuits of the proposed
converter for duty cycles smaller than 0.5 during the positive
half cycle. The waveforms of the proposed converter during
these conditions are shown in Fig. 9. The intervals of
operation are explained as follows.

Similarly, the ripple currents in Q3 and Q4 are the same as
the ripple current in series inductances L3 and L4:
(7)

L3/L4:
∆
(8)

a) Intervals 1 and 3: Body diodes of Q2 and Q4 conducting

Interval 3 [t2-t3]: At t2, Q1/Q2 are turned off, while Q3/
Q4 remain on, as shown in Fig. 6-c. During this interval, the
current in series inductances L3 and L4 increases linearly and
stores the energy in these inductors. The ripple currents in Q3
and Q4 are the same as the ripple current in series
inductances L3 and L4:
∆

1

(9)

The current in L1 and L2 decreases linearly and transfers the
energy to the load through D1, Co and body diode of Q2. The
ripple current in series inductances L1 and L2 is given by:
∆

1

b) Interval 2: Q1 and Q2 are “ON”, and body diode of Q4 conducting

(10)

L3/L4:
∆
1
(11)
Interval 4 [t3-t4]: At t3, Q3/Q4 remain on, while Q1/Q2 are
turned on, as shown I Fig. 6-b. During this interval, the
currents in the four inductors each increase linearly, storing
are the same as the ripple currents in L1 and L2:

(13)

L3/L4:
∆
(14)

(6)

∆

(12)

c) Interval 4: Q3 and Q4 are “ON”, and body diode of Q2 conducting
Fig. 8. BLIL PFC boost converter operating at D < 0.5

Interval 2 [t1-t2]: At t1, Q1/Q2 turn on, while Q3/Q4
remain off, as shown in Fig. 8-b. During this interval, the
current in series inductances L1 and L2 increases linearly,
storing energy in these inductors. The ripple currents in Q1
and Q2 are the same as the current in series inductances L1
and L2, where the ripple current is given by:
∆

(17)

and body diode of Q4. The ripple current in L3 and L4 is:
∆

(18)

The input ripple current is the sum of the currents in L1/L2
and L3/L4:
(19)
∆
Interval 3 [t2-t3]: At t2, Q1/Q2 are turned off, while Q3/Q4
remain off, as shown in Fig. 8-a. During this interval, the
current in series inductances L1 and L2 decreases linearly
and transfers the energy to the load through D1, Co and body
diode of Q2. The ripple current in series inductances L1 and
L2 is given by:
∆

(20)

Similarly, the current in the series inductances L3 and L4 also
decreases linearly, transferring the energy to the load through
D3, Co and body diode of Q4. The ripple current in series
inductances L3 and L4 is:
∆

(21)

The input current is the sum of currents in L1/L2 and L3/L4:
∆

Fig. 9. BLIL PFC boost converter steady-state waveforms at D < 0.5

Interval 1 [t0-t1]: At t0, Q1 and Q2 turn off, while Q3 and
Q4 remain off, as shown in Fig. 8-a. During this interval, the
current in series inductances L1 and L2 decreases linearly
and transfers the energy to the load through D1, Co and body
diode of Q2. The ripple current in series inductances L1 and
L2 is:
∆

(15)

In addition, the current in the series inductances L3 and L4
also decreases linearly, transferring the energy to the load
through D3, Co and body diode of Q4. The ripple currents in
series inductances L3 and L4 is:
∆

(15)

The input current is the sum of currents in L1/L2 and L3/L4:
∆

(16)

(22)

Interval 4 [t3-t4]: At t3, Q3/Q4 are turned on, while Q1/Q2
remain off, as shown in Fig. 8-c. During this interval, the
current in series inductances L3 and L4 increases linearly and
stores the energy in these inductors. The ripple currents in
Q3 and Q4 are the same as the current in series inductances
L3 and L4, where the ripple current is given by:
∆

(23)

and body diode of Q4. The ripple current in L1 and L2 is:
∆

(24)

L3/L4:
(25)
∆
The operation of converter during the negative input
voltage half cycle is similar to the operation of converter
during the positive input voltage half cycle.

V.

SIMULATION RESULT
TS

PSIM simulation software was used to v
verify steady state
waveforms of each component. Fig. 10 s
shows the PSIM
simulation circuits of the proposed BLIL PFC converter. As it
C
can be seen the power stage section of conv
verter consists of
four boost inductors – Ld1 to Ld4, four fas boost diodes –
st
Db1 to Db4, four switches – Q1 to Q4 and t
their body diodes
Dq1 to Dq4. Also it consists of two curren loops and one
nt
voltage loop. The sensed input voltage is m
multiplied by the

compensated output voltage, and then generates a control
signal to be compared with the switching career waveforms
to generate the gating signals for ma FETs.
ain
Fig. 11 shows the PSIM simulati results of a BLIL PFC
ion
boost converter. The input current is in phase with input
voltage, and it has close to unity power factor. Also the
y
output voltage is regulated at arou 400V, with a 120 Hz
und
low frequency ripple. The converte is operating at 70 kHz
er
switching frequency, 240 V input voltage and 3.4 kW output
v
power.

Fig. 10. PSIM simulation circuit for the proposed BLIL PFC boost converter
L
Fig. 11. Simulation waveforms for the proposed BLIL PFC boost converter
including output voltage, input voltage and in
nput current

VI.

EXPERIMENTA RESULTS
TAL

An experimental prototype, illust
trated in Fig. 12, was built
to verify the operation of the proposed converter. Fig. 13
shows the input voltage, input curren and PFC bus voltage of
nt
the converter under the following test conditions: Vin = 240
t
V, Iin = 15 A, Po = 3400 W, fsw = 70 kHz. The input current is
0
in line and phase with the input volt
tage, and its shape is close
to a sinusoidal waveform.
In order to verify the quality of the input current, its

is available from the mains feed to charge the batteries,
reducing charging time and electricity costs.
2.5

Harmonic Current (A)

2

EN 61000-3-2 Class D Limits (A)
Amplitude (A) Vin = 120 V

1.5

Amplitude (A) Vin = 240 V

1
0.5
0

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

harmonics up to 39th harmonic order are given and compared
with the EN 61000-3-2 standard. Fig. 14 shows the input
current harmonics versus harmonic numbers at full load for
120 V and 240 V input voltages. It is clearly shown that the
generated harmonics are well below IEC 61000-3-2 standard
for the input line harmonics which is required for PHEV
chargers. In Fig. 15, the input current total harmonics
distortions are given at full load and for 120 V and 240 V
input voltages. It can be noted that mains current THD are
smaller than 5% from 50% load to full load and it is
compliant to IEC 6100-3-2. Another parameter to show the
quality of input current is power factor. In Fig. 16, the
converter power factor is shown at full load for different
input voltages. As it can be seen, power factor is greater than
0.99 from 50% load to full load.

Harmonics Order
Fig. 14. Input current harmonics at full load for Vin = 120 V and 240 V

45
40
35
30

THD (%)

20 cm

25

Vin=240

20
15

Vin=120

10
5
Fig. 12. Breadboard prototype of BLIL PFC boost converter

3500

3500

2500

2000

1500

1000

3000

Input Voltage

3000

Output Voltage

500

0

0
Output Power (W)
Fig. 15. Total harmonics distortion vs. output power at Vin = 120V and Vin
= 240V
1.02
1

Vin=240

0.92
0.9

Vin=120

0.88
0.86
2500

2000

1500

0.84
1000

The efficiency of converter versus output power for
different input voltages is provided in Fig. 17. High
efficiency over entire load range is achieved in this topology,
enabling fewer problems with heat dissipation and cooling
systems. Furthermore, a higher efficiency means more power

0.94

500

Fig. 13. Proposed BLIL PFC experimental waveforms; Test Condition: Po =
3400W, Vin = 240V, Iin = 15A

0.96

0

Input Current

Power factor

0.98

Output Power (W)
Fig. 16. Power Factor vs. output power at Vin = 120V and Vin = 240V

100

[7]

99

[8]

98
Efficiency (%)

97
[9]

96
95

Vin=240 V

94

Vin=220 V

[10]

93
Vin=120 V

92

[11]

91

Vin=90 V
[12]
3500

3000

2500

2000

1500

1000

500

0

90

Output Power (W)
Fig. 17. Efficiency vs. output power at Vin = 90V, Vin = 120V, Vin = 220V
and Vin = 240V

VII.

CONCLUSION

A high performance AC-DC boost converter topology has
been presented in this paper for the front-end AC-DC
converter in PHEV battery chargers. The proposed converter
topology has been analyzed and performance characteristics
presented. A prototype converter was built to verify the
proof-of-concept.
The theoretical waveforms were compared with the
simulation results and the results taken from prototype unit.
Also some key experimental waveforms are given. Finally
input current harmonics at each harmonic order was
compared more explicitly with the IEC 6100-3-2 standard
limits. The total harmonics distortion and power factor was
measured on prototype unit and showed great results.
The converter topology shows a high input power factor,
high efficiency over entire load range and excellent input
current harmonics. It is an excellent option for single phase
PFC solution in higher power applications.

[13]
[14]
[15]

[16]
[17]
[18]
[19]
[20]
[21]

[22]

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