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2016 2017 ieee vlsi project titles

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2016 2017 ieee vlsi project titles - pvr technology

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2016 2017 ieee vlsi project titles

  1. 1. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 2016 - 2017 VLSI IEEE FINAL YEAR Projects S.NO IEEE 2016-17 VLSI Project Titles Domain Lang/Year 1 A Fully Digital Front-End Architecture for ECG Acquisition System LOW POWER VLSI/2016 With 0.5 V Supply 2 Low-Cost High-Performance VLSI Architecture for Montgomery LOW POWER VLSI/2016 Modular Multiplication 3 RF Power Gating: A Low-Power Technique for Adaptive Radios LOW POWER VLSI/2016 4 Low-Power ECG-Based Processor for Predicting Ventricular LOW POWER VLSI/2016 Arrhythmia 5 A New Parallel VLSI Architecture for Real-Time Electrical LOW POWER VLSI/2016 Capacitance Tomography 6 Low-Power FPGA Design Using Memoization-Based Approximate LOW POWER VLSI/2016 Computing 7 Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly LOW POWER VLSI/2016 Units 8 A High-Speed FPGA Implementation of an RSD-Based ECC HIGH SPEED DATA VLSI/2016 Processor TRANSMISSION 9 High-Speed and Energy-Efficient Carry Skip Adder Operating HIGH SPEED DATA VLSI/2016 Under a Wide Range of Supply Voltage Levels TRANSMISSION 10 A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage HIGH SPEED DATA VLSI/2016 and Frequency Scaling TRANSMISSION 11 Code Compression for Embedded Systems Using Separated HIGH SPEED DATA VLSI/2016
  2. 2. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 Dictionaries TRANSMISSION 12 A Dynamically Reconfigurable Multi-ASIP Architecture for Multi- HIGH SPEED DATA VLSI/2016 standard and Multimode Turbo Decoding TRANSMISSION Design and Implementation of High-Speed All-Pass HIGH SPEED DATA 13 Transformation-Based Variable Digital Filters by Breaking the VLSI/2016 TRANSMISSION Dependence of Operating Frequency on Filter Order AREA EFFICIENT/ 14 A Mixed-Decimation MDF Architecture for Radix-2K Parallel FFT TIMING & DELAY VLSI/2016 REDUCTION Algorithm and Architecture of Configurable Joint Detection and AREA EFFICIENT/ 15 Decoding for MIMO Wireless Communications With Convolution TIMING & DELAY VLSI/2016 Codes REDUCTION One-Cycle Correction of Timing Errors in Pipelines With Standard AREA EFFICIENT/ 16 TIMING & DELAY VLSI/2016 Clocked Elements REDUCTION Hardware and Energy-Efficient Stochastic LU Decomposition AREA EFFICIENT/ 17 TIMING & DELAY VLSI/2016 Scheme for MIMO Receivers REDUCTION AREA EFFICIENT/ 18 Hybrid LUT/Multiplexer FPGA Logic Architectures TIMING & DELAY VLSI/2016 REDUCTION A 520k (18 900, 17 010) Array Dispersion LDPC Decoder AREA EFFICIENT/ 19 TIMING & DELAY VLSI/2016 Architectures for NAND-Flash Memory REDUCTION Implementing Minimum-Energy-Point Systems With Adaptive AREA EFFICIENT/ 20 TIMING & DELAY VLSI/2016 Logic REDUCTION
  3. 3. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 High-Performance Pipelined Architecture of Elliptic Curve Scalar AREA EFFICIENT/ 21 TIMING & DELAY VLSI/2016 Multiplication Over GF(2m ) REDUCTION High-Performance NB-LDPC Decoder With Reduction of Message AREA EFFICIENT/ 22 TIMING & DELAY VLSI/2016 Exchange REDUCTION LUT Optimization for Distributed Arithmetic-Based Block Least AREA EFFICIENT/ 23 TIMING & DELAY VLSI/2016 Mean Square Adaptive Filter REDUCTION Graph-Based Transistor Network Generation Method for AREA EFFICIENT/ 24 TIMING & DELAY VLSI/2016 Supergate Design REDUCTION Flexible DSP Accelerator Architecture Exploiting Carry-Save AREA EFFICIENT/ 25 TIMING & DELAY VLSI/2016 Arithmetic REDUCTION A Cellular Network Architecture With Polynomial Weight AREA EFFICIENT/ 26 TIMING & DELAY VLSI/2016 Functions REDUCTION A High-Performance FIR Filter Architecture for Fixed and AREA EFFICIENT/ 27 TIMING & DELAY VLSI/2016 Reconfigurable Applications REDUCTION Fault Tolerant Parallel FFTs Using Error Correction Codes and AREA EFFICIENT/ 28 TIMING & DELAY VLSI/2016 Parseval Checks REDUCTION Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum AREA EFFICIENT/ 29 LDPC Decoding for MLC NAND Flash-Based Storage in Mobile TIMING & DELAY VLSI/2016 Device REDUCTION 30 Unequal-Error-Protection Error Correction Codes for the AREA EFFICIENT/ VLSI/2016 TIMING & DELAY
  4. 4. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 Embedded Memories in Digital Signal Processors REDUCTION AREA EFFICIENT/ 31 A High Throughput List Decoder Architecture for Polar Codes TIMING & DELAY VLSI/2016 REDUCTION A Normal I/O Order Radix-2 FFT Architecture to Process Twin AREA EFFICIENT/ 32 TIMING & DELAY VLSI/2016 Data Streams for MIMO REDUCTION Design and FPGA Implementation of a Reconfigurable 1024- AREA EFFICIENT/ 33 TIMING & DELAY VLSI/2016 Channel Channelization Architecture for SDR Application REDUCTION 34 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Audio, Image and VLSI/2016 Units for Video Encoding Video Processing 35 A Configurable Parallel Hardware Architecture for Efficient Audio, Image and VLSI/2016 Integral Histogram Image Computing Video Processing 36 A New Binary-Halved Clustering Method and ERT Processor for Audio, Image and VLSI/2016 ASSR System Video Processing 37 The VLSI Architecture of a Highly Efficient De-blocking Filter for Audio, Image and VLSI/2016 HEVC Systems Video Processing 38 Low-Power System for Detection of Symptomatic Patterns in Audio, Image and VLSI/2016 Audio Biological Signals Video Processing 39 In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers NETWORKING VLSI/2016 40 Source Code Error Detection in High-Level Synthesis Functional VERIFICATION VLSI/2016 Verification 41 A Single-Ended With Dynamic Feedback Control 8T Subthreshold TANNER /MICROWIND VLSI/2016 SRAM Cell – (AREA EFFICEINT)
  5. 5. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 42 OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its TANNER /MICROWIND VLSI/2016 Application – (AREA EFFICEINT) A Robust Energy/Area-Efficient Forwarded-Clock Receiver With TANNER /MICROWIND 43 All-Digital Clock and Data Recovery in 28-nm CMOS for High- VLSI/2016 – (AREA EFFICEINT) Density Interconnects 44 Full-Swing Local Bitline SRAM Architecture Based on the 22-nm TANNER /MICROWIND VLSI/2016 FinFET Technology for Low-Voltage Operation – (AREA EFFICEINT) 45 A 0.1–3.5-GHz Duty-Cycle Measurement and Correction TANNER /MICROWIND VLSI/2016 Technique in 130-nm CMOS – (AREA EFFICEINT) 46 A Low-Power Robust Easily Cascaded PentaMTJ-Based TANNER /MICROWIND VLSI/2016 Combinational and Sequential Circuits – (LOW POWER) 47 Low-Power Variation-Tolerant Nonvolatile Lookup Table Design TANNER /MICROWIND VLSI/2016 – (LOW POWER) 48 Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM TANNER /MICROWIND VLSI/2016 – (LOW POWER) 49 Frequency-Boost Jitter Reduction for Voltage-Controlled Ring TANNER /MICROWIND VLSI/2016 Oscillators – (LOW POWER) 50 High-Speed, Low-Power, and Highly Reliable Frequency TANNER /MICROWIND VLSI/2016 Multiplier for DLL-Based Clock Generator – (LOW POWER)
  6. 6. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 PROJECT SUPPORT TO REGISTERED STUDENTS: 1)IEEE Base paper. 2) Abstract Document. 3) Future Enhancement (based on Requirement). 4) Modified Title / Modified Abstract (based on Requirement). 5) Complete Source Code/Simulation File/ Hardware Kit. 6) How to Run execution help file. 7) Software Packages 8) International Conference / International Journal Publication based on your project.
  7. 7. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457
  8. 8. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457
  9. 9. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457
  10. 10. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457
  • salamsurjitsingh

    May. 26, 2017

2016 2017 ieee vlsi project titles - pvr technology

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