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A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT

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A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT

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A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT

  1. 1. Head office: 3nd floor, Krishna Reddy Buildings, OPP: ICICI ATM, Ramalingapuram, Nellore www.pvrtechnology.com, E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT Abstract This paper presents a mixed-decimation multipath delay feedback (M2 DF) approach for the radix-2k fast Fourier transform. We employ the principle of folding transformation to derive the proposed architecture, which activates the idle period of arithmetic modules in multipath delay feedback (MDF) architectures by integrating the decimation-in-time operations into the decimation-in-frequency-operated computing units. Furthermore, we compare the proposed design with other efficient schemes, namely, the MDF and the multipath delay commutator (MDC) scheme theoretically and experimentally. Relying on the obtained expressions and statistics, it can be concluded that the M2DF design serves as an efficient alternative to the MDF scheme, since it achieves improved efficiency in the utilization of arithmetic resources without deteriorating the superiorities of feedback structures. In addition, the recommended design performs better in memory requirement and computing delay compared with the MDC approach. Tools:  Modelsim 6.4b  Xilinx ISE 10.1 Languages:  VHDL/Verilog HDL

A Mixed-Decimation MDF Architecture for Radix-2k Parallel FFT

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