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E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457
VLSI Design for Convolutive Blind Source
Separation
Abstract
This brief presents an efficient very-large-scale integration architecture design for
convolutive blind source separation (CBSS). The CBSS separation network derived from the
information maximization (Infomax) approach is adopted. The proposed CBSS chip design
consists mainly of Infomax filtering modules and scaling factor computation modules. In an
Infomax filtering module, input samples are filtered by an Infomax filter
with the weights updated by Infomax-driven stochastic learning rules. As for the scaling factor
computation module, all operations including logistic sigmoid are integrated and implemented by
the circuit design based on a piecewise-linear approximation scheme. The proposed prototype
chip is implemented via a semi-custom design using 90-nm CMOS technology on a die size of
approximately 0.54 × 0.54 mm2.
Tools:
 Modelsim 6.4b
 Xilinx ISE 10.1
Languages:
 VHDL/Verilog HDL

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VLSI Design for Convolutive Blind Source Separation

  • 1. E-Mail: pvrieeeprojects@gmail.com, Ph: 81432 71457 VLSI Design for Convolutive Blind Source Separation Abstract This brief presents an efficient very-large-scale integration architecture design for convolutive blind source separation (CBSS). The CBSS separation network derived from the information maximization (Infomax) approach is adopted. The proposed CBSS chip design consists mainly of Infomax filtering modules and scaling factor computation modules. In an Infomax filtering module, input samples are filtered by an Infomax filter with the weights updated by Infomax-driven stochastic learning rules. As for the scaling factor computation module, all operations including logistic sigmoid are integrated and implemented by the circuit design based on a piecewise-linear approximation scheme. The proposed prototype chip is implemented via a semi-custom design using 90-nm CMOS technology on a die size of approximately 0.54 × 0.54 mm2. Tools:  Modelsim 6.4b  Xilinx ISE 10.1 Languages:  VHDL/Verilog HDL