1. Shreyas Jayantilal Charola
Mobile : +91-9662772266 E-Mail id : patel.shreyas2012@gmail.com
My immediate aim is to gain work experience and learn the current trends of ASIC & FPGA
verification and design and expand my horizon while working as an ASIC design/verification
engineer and work with full capacity and dedication for the concerned organization.
ACADEMIA
Sr.
No.
Course Discipline / Specialization Board / University
Percentage
(%)
Year of
Passing
1. M.Tech VLSI Design
Vellore Institute Of
Technology University
89.5 2014
2. B.E. Electronics and Telecommunicaton Saurashtra University 68.33 2011
TECHNICAL SKILLS
EDA Tools
 ASIC Design Tools (Cadence and Tanner)
 Simulation : NC Sim
 Synthesis : RTL Complier
 Placement and routing : Encounter
 Full Custom Tools
 Schematic : Virtuoso, S-edit
 Layout : L-Edit
Hardware Description Languages Verilog, VHDL
Assembly Languages Microprocessor 8085,Microcontroller 8051
FPGA Xilinx, Altera Quartus II
Simulation Software Keil, ModelSim, Matlab,MultiSim,Proteus,TINA
PROJECT GUIDED
2016 - 2017: Recently Abhishek Parekh studying in Master of Technology at Marwadi Education Group Of
Institute is working Different type of Low Power Efficient Adiabatic Logics Circuits approach
to achieve large power reduction and improve device performance of low power VLSI chip.
AREA OF INTEREST/ SPECIALIZATIONS
1. Low power VLSI Design
2. FPGA based Design
3. Digital VLSI Design

2. ACADEMIC PROJECTS
 PG Project :
Title : A Novel Approach to Implement Low power Arcitecture MLP Neural Network
for speech recognition.
Duration : Dec’13 – May’14
Description : Motivation of doing this project to reduce area and power with modified Multi
Layer Neyral Network architecture using to different approach, they are Banking
organigtion and Bipartitle tabular method.
Title : Optimize Design Platform for High Speed Digital Filter Using Folding Technique.
Duration : Jul’12 – May’13
Descriptio : Motivation of doing this project to minization number of register used in DSP
filter and also reduce the time-to market pressure for RTL design engineer.
 UG Project :
Title : Weighing Scale Automation using RFID.
Duration : Aug’10 – Apr’11
Description : Main aim of project to transfer the analog weighted data by loadcell (Instrument
to measure the weight of any object almost used in shop) to lcd which placed at
receiver side using RFID.
CONFERENCE, WORKSHOP & STTP ATTENDED
1. TEQIP – II sponsored and IETE sponsored Two day finishing school on “wireless sensor network”,
September- 2015 SVNIT, Surat.
2. TEQIP – II sponsored and IETE sponsored and JAMPOT photonics Pune supported Two day on
Industry-Institute Programme on "Embedded Systems in Robotics”, September- 2015 SVNIT, Surat.
3. Attended Four day FDP on "Design Engineering" on 19th to 22nd February, 2016.
4. IEEE sponsored and IETE sponsored One day workshop on “HAM Radio”, July- 2016 Marwadi
University, Surat.
RESEARCH PUBLICATIONS
1. Shreyas Patel , Prof.J.S. Rani Alex "Optimized Design Platform for High Speed Digital Filter
using Folding Technique" Published in IJRECT, ISSN Print: 2348-0017 ISSN Online: 2347-6109
Volume No.2 Issue No.1 January-February, 2014.
2. Shreyas Patel, John Sahaya Rani Alex and Nithy Venkatesan "Low-Power Multi-Layer Perceptron
Neural Network Architecture for Speech Recognition" published in Indian Journal of Science and
Technology, ISSN (Print) : 0974-6846 ISSN (Online) : 0974-5645,Vol 8(20),August 2015.

3. ACHIEVEMENTS
1. Deliver Expert talk on "Mixed signal VLSI Design" two days National workshop at GLA
University, Mathura on 5th-6th February,2016.
2. Secured 2nd Rank in set conference held at Vellore Institute of technology and Research paper got
selected International Journal of Research in Electronics & Communication Technology. Volume-2,
Issue-1, January-March, 2014, pp. 19-30, © IASTER 2013 (ISSN Online:-2347-6109).
3. Secured "B" grade for Communicative English-LAB, Rajkot.
4. Secured 1st rank in Group Discussion Competition Dextrous'10, Rajkot
SUBJECTS TEACHING AT U.G. LEVEL
1. Digital Electronics
2. VLSI Design
3. Basic Electronics and Circuits
4. Electronics Measurment and Instrumentation
5. Design Enginnering
6. Mechatronics
SUBJECTS TEACHING AT P.G. LEVEL
1. Digital VLSI Design
2. Low power VLSI Design
REFERENCE
Mr. Vishal Bhimani
Designation: Design and Verification Engineer at
Cadence.
Place: Bangalore
Contact No. : 09986547076
E-Mail: vishalbhimani77.vb@gmail.com
Mr.Ketan Sanjay Chougule
Designation: Analog Engineer at Intel Pvt.
Ltd.
Place: Bangalore
Contact No. :
E-Mail: ketan.s.chougule@intel.com
Dr. Rajendrakumar Patel
Designation: Associate Professor and HOD
Marwadi University
Place: Rajkot
Contact No. : 09687680267
E-mail:
rajendrakumar.patel@marwadieducation.edu.in
Prof.John Sahaya Rani Alex
Designation: Associate Professor
Vellore University
Place: Chennai
Contact No. : 9824416484
Email:
jsranialex@vit.ac.in

4. EXPERIANCE
1. 1 Year and 7 Month Work experience as a Teaching Assistant along with very experienced and
renowned faculty at Dept. of ELECTRONICS AND COMMUNICATION at Sardar Vallabhai
National Institute of Technology (NIT),Surat.
2. Started Working as Assistant Proffesor at Marwadi Education Foundation’s Group of Institutes
(MEFGI) on 20th January 2016 ,Rajkot.
TRAINING
1. Took part in Industrial automation training at "NCVT Institute Private Limited" at Rajkot.
2. Attended training session by "Videocon Industries Limited" at Bharuch.
STRENGTH
1. Displaying scholarly traits and being supportive
2. Good listener
3. Silent
HOBBIES
1. Volleyball
2. Social Service
PERSONAL VITAE
Date of Birth : 3th April,1990.
Address (Per.) : Sarita App, B/No-101,University Road,Rajkot –360005.
Dist:- Rajkot State:- Gujarat
Alternative email ID : shreyas.charola@marwadieducation.edu.in
Languages Known : English, Hindi and Gujarati (Read, Write and Speak)
DECLARATION
I hereby declare that the information furnished above is true to the best of my knowledge and
understanding.
Your Truely
Place:Rajkot (Charola Shreyas Jayantilal)