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Digital filter design using VHDL

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Digital filter designing details using VHDL
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Digital filter design using VHDL

  1. 1. .w I] T
  2. 2. PRESENTED BY o ARINDAM KANODIA (14200311010) o ARKO DAS (1420031 1012) o AVIK KUMAR KUNDU (14200311014) o PIJUS KAPRI (1420031 1031) UNDER THE GUIDANCE OF PROF. SUDIPTA GHOSH
  3. 3. L OUTL| IIE ç; - INTRODUCTION -. :,: TYPES OF FILTERS 8. THEIR DISCUSSION : år VHDL- THE LANGUAGE af. : IMPLEMENTATION & ANALYSIS OF SUB BLOCKS IMPLEMENTATION & ANALYSIS OF FIR FILTERS 2.? CONCLUSION : if: FUTURE PLAN
  4. 4. I l INTRODUCTION å o Electrical filters are used to remove of I contaminating ⁄ unwanted signals. F o In electrical filters, we take advantage of the filter's . __- differenf responses at different frequencies, and E? ' the fact that many signals that are corrupted by noise have a signal and noise that have different frequency content.
  5. 5. FILTER o Analog Filter -> Lowpass ->Highpass ->Bandpass o Digital Filter -> lIR -> FIR
  6. 6. 41 TYPES OF DIGITAL FILTER IIR Filter FIR Filter
  7. 7. El lIR FILTER ADVANTAG ES They are economical in their use of delays, multipliers and adders DISADVANTAGES They are sensitive to coefficient round- off inaccuracies and the effects of overflow in fixed point arithmetic. These effects can lead to instability or serious distortion
  8. 8. ål FIR FILTER ADVANTAG ES These structures are always stable, and because there is no recursion, round-off and overflow errors are easily controlled DISADVANTAGES Large orders can be required to perform fairly simple filtering tasks
  9. 9. COI, ⁄IP⁄-RISOII OF IIR AND FIR FILTERS FIR Filter IIR Filter x(n) 1 h. ,(n) yln) ›<(n) i h. ,(n) y(n) ›-, « ›- ›-, - a- Xlz) B(z) Y(Z) XIZ) , I B(z) Ylz) h. .(n) l< A(z)
  10. 10. EI DESIGN PROCEDURE OF IIR FILTERS Analog g l Analog Digital Prototype T ”i Filter ' i i *I Filter Filter i I
  11. 11. Equivalent discrcte-time ñIler Mapping for method Gmäuia Backward dilTerence method This method is not recommended, because the discrcte-time equivalent may become unsmblc. METHODS FOR ANALOG ro '“°"'°“ Bilinear DIGITAL 36333310« CONVERSION 'Mum prewarptng impulse- invnriance method Apoleoruroatr- -a is mnpped to: : 2"'. An infinite pole or zero is mnpped to z = -l. Mntchcd pole- wo mnpping method
  12. 12. TYPES OF ANALOG PROTOTYPE FILTERS oButterworlh Filter oChebychev Filter oElliptic Filter
  13. 13. L BUTTERWORTH FILTER Butterworth ensures a flat response in the passband and an adequate rate of rolloff Analog Buttcmronlupliiirfcfrd e 1 » E 1.31 1 I å 4 n _ n: . >. (AI o I = I 1 u. i N: å'_n N54 "(77 å), Å _. _ w Ii ao rs l: m 0 u
  14. 14. ELLIPTIC FILTER o This filter has equiripple (the same amount of ripple in the passband and stopband) I GI OC 0.7 0D OJ O4 08 08 0.!
  15. 15. L Cl-IEBN/ CI-IEV FILTER a The Chebychev filter has ripple in the passband of the filter Analog Chebychev Type I Filter . , _--. n. . 'wwwi- I , T x ⁄› S-: -J ' - 1 . g i , E 0.24 . å O. , g r n: Å ›, 0.4 . å N: z : I 1 I v: å' n. : 1 . u. N = s"- N - 4 ° . . . :n . .. " 0 w. . ' "T Frequency a)
  16. 16. L : ECTS OF POLIES , ,1>= y1'D EEROS Åiár- - pnInx I [Frem l - Effect of addition of poles The general effect of addition of a pole is a tendency to shift the locus towards right side of s-plane and this lowers the stability.
  17. 17. BILINEAR TRANSFORMATION oDEFlNED BY: u1z)= n,(â"= ") 1;1+z"
  18. 18. IIR FILTER REALIZATION o Direct y1n1 = å b1k1- xrn - k1- åark) - vin - k1 k-O o Cascade
  19. 19. å) DI R E CT R EA LI Z⁄%1' I O N b[N-1] , L a) at an: er* 1 1 1)) 14.)) 4- DIN] -i r - - recursive part A(z) B(z) - non-recursive part
  20. 20. CI C / GXS C / ⁄'II' / öx I. . I Z/ /ix-I" O III 1-I( ) i bIZ-I l-l ñ (1 _ Ghz-I › B(z) z = a? = . az-e = - ajZ-j o H (1 _ pjZ-l) _ J-O
  21. 21. g V I-I D L- TH E L/ ÅX NG UAG E Industry standard language used mainly for academic purposes The language not only defines the syntax but also defines very clear simulation semantics for each language construct o It's very useful in teaching top-down dedgn
  22. 22. å PROPOSED SCI-IEIVIE In order to meet the performance parameter and design on the basis of implementation platform of finite impulse response filters different schemes are proposed under VHDL language Bit Parallel Arithmetic o Bit Serial Arithmetic
  23. 23. BIT PARALLEL ARITHMETIC ADVANTAGE The amount of work performed by a processing element during one clock cycle is relatively large, and the clock frequency can therefore be kept low. It means it has high Computational speed. DISADVANTAGE It has high power consumption and chip area as compared to bit-serial arithmetic.
  24. 24. Bit-parallel ripple-carry adder xWd-l . YWd-l
  25. 25. ål BIT SER AL AR| TI*-I1⁄1ET| C ADVANTAGE Bit serial digital filters have less power consumption because of serial parallel multiplier. Also it consumes smaller area compared to bit parallel. DISADVANTAGE The design time for the bit-serial system increases due to the higher complexity of timing the bit-serial streams
  26. 26. Bit-serial adder and substractor
  27. 27. L LEVELS OF ABSTR ACTION Data Flow Level Structural Level Behavioural Level
  28. 28. lmgolemenlcrllor) of sub blocks r) Half adder Full adder o Multiplexer 4 bit ripple carry adder en D flip flop 4 bit shift register si) Shift and add Multiplier
  29. 29. IMPLEMENTATION OF HALF- ADDER USING VHDL
  30. 30. 1 1 IMPLEMENTATION or HALF-ADDER USING VHDHCONTINUED) Signalnane Value H-Içor"zço-Hsço-"tço-“oço Inpuls »a 1 i i)) ; T1212 outputs osum om ocarn' 1 I I
  31. 31. CçJr 01101001. c; sur. ) g 001100114! r. e d d a m F _
  32. 32. IMPLEMENTATION o): FULL-ADDER USING HALF-ADDERKZONTINUED) Syndrom Vu inputs oa
  33. 33. å IIVIPLEIVIEIVT/ ÅTIOIV OF 16><1 MUX USING 8x1 lvl >< Vi MMM u une
  34. 34. i. ;”-, , -. ,, , , _, “sc, ,n, ,_W. )_UÆmÆt 2*t0;trüy11tjtt?1ñru1,ñrtgfpttgtyrtgilriuirt * ;51 1 : i ;1 , ;3 L; 1; j; i_. ,_, ñ"i; T; .; * = i en )lIJ)i « T4 .11)111.1L1TJ1 )%gh; m,hNL gâpijlâlgërâipnitrñuiir §Å; n;nhn, ngn; m;ngnpn; r;njwL 111) ⁄ i 1") 'TU 1 l) 1 1) 1 T 1. T ;17 1") 1 1
  35. 35. CI | M P LE lvl) E NTA TI O N O F 4- B IT R | R R L E C ⁄- R R Y fx. D D E R U S I N C3 V H DL
  36. 36. l I I livtPLEIVIEIVTATIOPI or . ⁄.: -011 RIPPLE CARRY ADDER USING VHDHCONTD) Swim: vane H v? - "rw 'u= "1')° "“. “""? ""'? °" "33 ' er* ITIDUIS Ij m1): 0 ' >3[2'1 0 ' Mill 1 »en o Æ , _ . I ° 4 3 369999963999 'I 399899630 M132 1 0312i 1 m1)) 0 ' r›:1OE outputs 02m l IEX osumili l . su-mizz 1 osumt): 1 -sunzüz o *Gårn 0 I
  37. 37. IMPLEMENTATION OF D- FLIPFLOP USING VHDL
  38. 38. liv“IPLE1/ '1ElITATlOIl or D-FLIPFLOP USING VHDL(CONTIIIUED) Now: ns 'U115 111 111115 335 413115 I I I 1111111111111)) 1)) 1))) 11))) 1 1 1 1
  39. 39. 41 l 1V) P | _E1⁄)E)'1'⁄%T| ON O F ⁄-i--B IT I-IIFT REGISTER USING VHDL BID' (Binary/ BCD) UID' (Up/ Down) Mode of Operation Binary Up Counter (0000-›0001-›. ..-›1111-›0000.. .) Binary Down Counter (1111-›1110-›. ..-›0000-›1111.. .) BCD Up Counter (0O00-›0001-›. ..-›1001-›000O. ..) BCD Down Counter (1001-›1000-›. . . -›0000-›1001 . ..)
  40. 40. Ii⁄lPLE1⁄iEl1TATION OF 4-BIT SHIFT REGISTER USING VHDL(CONTINUED)
  41. 41. I I 11V)PLE1VlElIT, AT| Ol1 OF SHIFT 8; ADD IVtULTIPLIER USING VHDL
  42. 42. liv)PLEiviE)'T/4'I'| O)' o): 31-1111) / A/DDD MULIIPLIER USING Vl-IDL (CONTIIVUED) a(4:1) y(8:1) b(4:1) clk
  43. 43. .I›I. l I I I I [›I
  44. 44. IMPLEMENTATION OF FIR FILTER
  45. 45. 14 Direct' form recalizcriion Transpose direct form FIR realization
  46. 46. SCHEMATIC DIAGRAM
  47. 47. fu iet ma: 9101:« ; cute Zum. 'giv-dm- 54v “Q ; DUEOIBDIQBIBIRBRIBIÅM SBBWWIIIQ' BE HTDI 9BTEIÅAQSIQBOIR$9XXP CIRCUIT DIAGRAM
  48. 48. PROJECT SLJivxivxivxxëxRY *Øüesm Uvemew : z: Summary F Jurçu Øhav: ardwavrungs 2 Syrthesxs Message: F) Tumsielm Messages 3 Map Messages 3 Hate and Rode Message: 3 Tirmo Message: 1 E ' ' 2 Al Curent Messages Øüdakd Report: 2 Sydhesns Report . Propel Ptopettie: Enable Erhanced Design Summary D Enable Message ñhemg D Display Irøetnedd Message: Enhanced Design Smwnuy Conlerds D Show Ena: D Show Wamangs D Show FaWng Cmsuanrds D Show Clock Report Project Fñe: "alle Name'. Fund Device: Product Version: Logic Utmzalioøn Number of Shces Nurnbet d Since FYp Flops Nurbet of 4 m] LUT: Nurber ol bondedlüBs Nurnbet of GCLX: Slam Culeri Report Name Sgnthezx: Rem! Iranslalim Report Mao Revo« Place and Route Recon Stahc Tun-ung Repocl 819m Report Dekhajaak uze Culent State'. oouzterjjü 0 Enou: xc2si5-öcs1 4t c Watnirugs: ISE,81n - Updated: Device Ulüization Summary [eslimatod values) llted Available . .- -Owavv Ddaüed Reports Generated Eau: Wed May 2D 1420,03 2015 Swhesized WedMay201U8512015 -sååå Warning: Utñizatiovl Info: R3 11%
  49. 49. ll l CONCLUSION o This current work is dealing with an approach to design and implementation of very fast fixed-function digital filters using bit-serial and bit-parallel arithmetic g- i f- o The main concerns 0t the filter designs are , TA " high throughput, small chip area and low power consumption. The increased throughput can be traded for reduced power consumption through power supply voltage scaling
  50. 50. THANK YOU

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