VIVADO user Guide

1. VIVADO PROJECT
STEP BY STEP

2. Step 1: Create a Vivado Project
Figure 1. Vivado Start-Up Window
Figure 2. Create Project

3. Step2: Set Project Name and Location

4. Step-3: Select Project Type (Allways RTL)

5. Step-4: Add/ Create Source

6. Create or Add IP (Optional)

7. Add Constrains ( No need any Action)

8. Step-5: Slect Parts : FPGA Board

9. Select Parts

10. Select Board

11. Finishing Steps

12. VIVADO Project Window

13. Step-6: Edit The Project - Create source files

17. Step-7: Define Module

20. Now, you can type your verilog code in the
window:
`timescale 1ns/1ps means that all the delays that follow (like# 5.1234) are interpreted to be in nanoseconds and any fractions
will be rounded to the nearest picosecond (5123ps).

23. Test Bench Code (Select Simulation Source and name as
andgatetest like this...