Interconnection Mechanisms Performance Models

1. Interconnection Mechanisms
Performance Models

2. Connecting Processors and Memories
• Shared Buses
• Interconnection Networks
• Static Networks
• Dynamic Networks
slide 2
P P P P
M M M
Interconnection Network
M
M M M
P P P P
M M M
Interconnection Network
M
M M M
Global Interconnection Network
M M M

3. Shared Bus
slide 3
each processor sees this picture:
processing
bus access
timentransactiobustimeprocessing
timentransactiobus
nutilizatiobus
+
== ρ
prob of a processor using the bus = ρ
prob of a processor not using the bus = 1 – ρ
prob of none of the n processors using the bus = (1 – ρ)n
prob of at least one processor using the bus = 1 – (1 – ρ)n
achieved BW on a relative scale = 1 – (1 – ρ)n
required BW = n ρ available BW = 1

4. Effect of re-submitted requests
slide 4
A W
ρ (1-PA )1- ρ + ρPA 1-PA
PA
( ) ( )
( ) ( ) ( )
( )
( )ρ
ρ
ρ
ρ
ρ
ρ
ρ
ρ
ρρ
ρ
ρρρρ
ρ
ρ
ρρρ
−+
=⇒=−−==
−+
=
−+
−+
−+
=
+==
−=
−+
=
−+
=
1
also11
11
1
1
raterequestactual
1
11
a
a
A
n
a
AA
A
A
A
wA
AW
A
A
AA
A
A
aPanBW
PP
P
P
P
qqa
qq
P
P
PP
P
q
prob = qA prob = qW

5. Shared Bus :BWper proc
-0.100
0.000
0.100
0.200
0.300
0.400
0.500
0.600
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
BW required (req probability)
BWachieved
n = 2
n = 3
n = 4
n = 2
n = 3
n = 4

6. Shared Bus :utilization
-0.200
0.000
0.200
0.400
0.600
0.800
1.000
1.200
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
req probability
utilization
n = 2
n = 3
n = 4
n = 2
n = 3
n = 4

7. Waiting time
slide 7
[ ]
bus
a
a
bus
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A
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Abus
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Abus
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1

8. Switched Networks
BUS
• Shared media
• Lower Cost
• Lower throughput
• Scalability poor
Switched Network
• Switched paths
• Higher cost
• Higher throughput
• Scalability better
slide 8

9. Interconnection Networks• Topology : who is connected to whom
• Direct / Indirect : where is switching done
• Static / Dynamic : when is switching done
• Circuit switching / packet switching : how are
connections established
• Store & forward / worm hole routing : how is the path
determined
• Centralized / distributed : how is switching controlled
• Synchronous/asynchronous : mode of operation
slide 9

10. Direct and Indirect Networks
slide 10
P
M
P
M
S
P
M
S
S
M
P
S
M
P
P
M
P
M
P
M
SWITCH
DIRECT
INDIRECT
node node
node node
link
link
link link
node
node
node
node
link
link
link
link

11. Static and Dynamic Networks
• Static Networks
• fixed point to point connections
• usually direct
• each node pair may not have a direct connection
• routing through nodes
• Dynamic Networks
• connections established as per need
• usually indirect
• path can be established between any pair of nodes
• routing through switches
slide 11

12. Static Network Topologies
slide 12
Linear
Star
2D-Mesh
Tree
Non-uniform connectivity

13. Static Networks Topologies-
contd.
slide 13
Ring
Fully Connected
Torus
Uniform connectivity

14. Illiac IV Mesh Network
slide 14
0 1 2
3 4 5
6 7 8
0
1
2
3
45
6
7
8
neighbors of node r :
(r ± 1) mod 9 and
(r ± 3) mod 9 Chordal Ring

15. Fat Tree Network
slide 15

16. Dynamic Networks
slide 16
k × k
cross -bar
switch
building block for multi-stage
dynamic networks
2 × 2
switch
straight exchange upper
broadcast
lower
broadcast
simplest
cross-bar

17. Baseline Network
slide 17
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
blocking can occur

18. Benes Network
slide 18
non-blocking

19. Switching Mechanism
• Circuit Switching (connection oriented
communication)
• A circuit is established between the source and the
destination
• Packet Switching (connectionless communication)
• Information is divided into packets and each packet is
sent independently from node to node
slide 19

20. Routing in Networks
slide 20
node
incoming
message
outgoing
message
header payload/data
store & forward
routing
worm hole
routing
time
BW
H
BW
l






+×=
BW
l
BW
H
nlatency
BW
l
BW
H
nlatency +





×=

21. Routing in presence of congestion
• Worm hole routing
• When message header is blocked, many links get
blocked with the message
• Solution: cut-through routing
• When message header is blocked, tail is allowed to
move, compressing the message into a single node
slide 21

22. Routing Options
• Deterministic routing: always same path followed
• Adaptive routing: best path selected to minimize
congestion
• Source based routing: message specifies path to
destination
• Destination based routing: message specifies only
destination address
slide 22

23. Some Performance
Parameters
slide 23
time
sender
receiver
time of flight
overhead
overhead
Tx time=bytes/BW
Tx time=bytes/BW
transport latency
total latency

24. Other Parameters
• Throughput ≈ Bandwidth (no credit for header)
• Bisection bandwidth = BW across a bisection
• Node degree
• Network Diameter
• Cost
• Fault Tolerance
slide 24

25. Multidimensional Grid/Mesh
Size
=k × k × …. × k (n times)
= k n
Diameter
= (k-1) × n without end around
connections
= k × n /2 with end around
connections
slide 25
k-ary n-cube
for (Binary) Hypercube : k = 2

26. Grid/Mesh Performance - 1
slide 26
cycleainreqmessageofprobis
dimensiononealong
hopsofno.av.is
dimensionsofnumberis
ratearrivalMessage
r
k
n
knr
d
d=
=
λ
kd

27. Grid/Mesh Performance - 2
n
p
Tkr
T
n
sd
s
2
linkaalong
requestofyProbabilit
2
OccupancyServer
2
rateService
ρ
µ
λ
ρ
µ
=
==
=
slide 27

28. Grid/Mesh Performance - 3
slide 28
k-ary n-cube
sw
w
T
pp
T
D
T
)1(2)1(2
)(1
modelqueueopen1//Muse
nodeaattimewaiting
B
ρ
ρ
ρ
ρρ
λ −
−
=





−
−
=
=

29. Switch Performance
slide 29
k × m
cross -bar
switch
m
m
m
m
m
mm
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timeservicesamerequirespacket)(or
mesageeachthatassumedisitHere
cycleserviceoneduringport
inputanatrequestofprobLet

30. Switch Performance – contd.
slide 30
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31. Switch Performance – contd.
slide 31
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32. Effect of re-submitted requests
slide 32
( )
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1
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'raterequestactual
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33. Effect of buffering
There are two possibilities
• Buffering before switching (k buffers, one at each
input port)
• Buffering after switching (m buffers, one at each
output port)
slide 33

34. Switch with input buffers
Rate of messages at input and output of each
queue is same in steady state - r per cycle
Service time includes delays due to conflicts,
calculated as earlier. This has an
exponential distribution – recall the analysis for a
shared bus.
M/M/1 open queue model can be used to calculate
queuing delay. Details are omitted.
T
P
P
A
A−1
slide 34

35. Switch with output buffers
Here we assume that all the messages destined for same
output are queued in the same buffer, in some order. That
is no rejections and no re-submissions.
For each queue,
Messages arriving per service cycle = ρ =
Prob of a request coming from one of
the k sources = p =
Apply MB/D/1 model for finding queuing delay Tw
m
kr
m
r
slide 35
T
p
Tw
)1(2 ρ
ρ
−
−
=