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LTspiceを活用した整流回路シミュレーション
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Tsuyoshi Horigome
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LTspiceを活用し、整流回路シミュレーションを行いました。出力の電解コンデンサのESRの影響をリップル波形にて波形検証を行っています。
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LTspiceを活用した整流回路シミュレーション
1.
All Rights Reserved
Copyright (C) Bee Technologies Corporation 2011 LTspice を活用した整流回路シミュレーション 株式会社ビー・テクノロジー http://www.beetech.info/ 2011 年 6 月 9 日 電解コンデンサの ESR の影響を検証する
2.
3.
1. AC Input
Voltage All Rights Reserved Copyright (C) Bee Technologies Corporation 2011
4.
5.
2. Case1: Ripple
Output Voltage with Small ESR All Rights Reserved Copyright (C) Bee Technologies Corporation 2011
6.
7.
3. Case2: Ripple
Output Voltage with Large ESR All Rights Reserved Copyright (C) Bee Technologies Corporation 2011
8.
9.
4. Comparison Result
All Rights Reserved Copyright (C) Bee Technologies Corporation 2011 Vripple Measurement Simulation Case1: @ESR=21.7496m 297.47 (mV) 297.97 (mV) Case2: @ESR=1000m 297.47 (mV) 617.53 (mV)
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