LinkedIn emplea cookies para mejorar la funcionalidad y el rendimiento de nuestro sitio web, así como para ofrecer publicidad relevante. Si continúas navegando por ese sitio web, aceptas el uso de cookies. Consulta nuestras Condiciones de uso y nuestra Política de privacidad para más información.

LinkedIn emplea cookies para mejorar la funcionalidad y el rendimiento de nuestro sitio web, así como para ofrecer publicidad relevante. Si continúas navegando por ese sitio web, aceptas el uso de cookies. Consulta nuestra Política de privacidad y nuestras Condiciones de uso para más información.

Se ha denunciado esta presentación.

¿Recomiendas esta presentación? ¿Por qué no compartes?

- faults in digital systems by dennis gookyi 15680 views
- Verilog hdl design examples by dennis gookyi 4602 views
- PLA Minimization -Testing by Dr.YNM 17478 views
- UNIT I- CPLD & FPGA ARCHITECTURE & ... by Dr.YNM 51529 views
- UNIT II-Programming in Linux by Dr.YNM 3668 views
- Vlsi physical design-notes by Dr.YNM 26699 views

test generation

Sin descargas

Visualizaciones totales

6.695

En SlideShare

0

De insertados

0

Número de insertados

3

Compartido

0

Descargas

409

Comentarios

0

Recomendaciones

22

No hay notas en la diapositiva.

- 1. Chapter 3: Test Generation
- 2. Fault Diagnosis of Digital Systems • Digital systems, even when designed with highly reliable components, do not operate for ever without developing some faults • When a system ultimately does develop a fault it has to be detected and located so that its effect can be removed • Fault detection means the discovery of something wrong in a digital system or circuit • Fault location means the identification of the faults with components, functional modules or subsystems, depending on the requirements • Fault diagnosis includes both fault detection and fault location
- 3. Fault detection • Fault detection in a logic circuit is carried out by applying a sequence of test inputs and observing the resulting outputs • the cost of testing includes the generation of test sequences and their application • One of the main objectives in testing is to minimize the length of the test sequence
- 4. Cont.
- 5. Test Generation for Combinational Logic Circuits • There are several methods available for deriving tests for combinational circuits • All these methods are based on the assumption that the circuit under test is non-redundant (A circuit is said to be non-redundant if the function realized by the circuit is not the same as the function realized by the circuit in the presence of a fault) and only a single stuck-at fault is present at any time
- 6. Cont. Some of the methods available for combinational circuits testing include: • One dimensional path sensitization • Boolean difference
- 7. One-dimensional Path Sensitization • The basic principle involved in “path sensitizing” is to choose some path from the origin of the failure to the circuit output • The path is said to be “sensitized” if the inputs to the gates along the path are assigned values so as to propagate the fault along the chosen path to the output.
- 8. Example: • Let us consider the circuit shown below and suppose that the fault is line X3 s-a-1
- 9. Solution (the forward trace) • This process of propagating the effect of the fault from its original location to the circuit output is known as the “forward trace”. • To test for X3 s-a-1, X5 and G2 must be set at 1 and X3 set at 0 so that if the fault is absent. • We now have a choice of propagating the fault from G5 to the circuit output Z via a path through G7G9 or through G8G9 • To propagate through G7G9 requires the output of G4 and G8 to be 1 • If G4=1, the output of G7 depends on the output of G5 and similarly if G8=1, the circuit output depends on G7 only
- 10. Solution (the backward trace) • The next phase of the method is the “backward trace”, in which the necessary gate conditions to propagate the fault along the sensitized path are established • For example, to set G4 at 1 both X1 and G1 must be set at 1; G1=1 implies X2=0 • In order for G2 to be 1, X4 must be set at 0 • For G8 to be 1, G6 must be 0, which requires either X2=0 or G3=0 • Since X2 has already been specified as 0, the output of G6 will be 0
- 11. Cont. • It is worth noting that G6 cannot be set at 0 by making G3=0, since this would imply X3=0, which is inconsistent with the previous assignment of X3 • Therefore the test X1X2X3X4X5=10001 detects the fault s-a-1, since the output of Z will be 0 for the fault-free circuit and 1 for the circuit having the fault. • The flaw in the one-dimensional path sensitization technique is that only one path is sensitized at a time
- 12. Boolean Difference • The basic principle of the Boolean difference is to derive two Boolean expressions – one of which represents normal fault-free behavior of the circuit and the other represents the logical behavior under an assumed single s-a-1 or s-a-0 fault condition • These two expressions are then exclusive ORed; if the result is 1 a fault is indicated.
- 13. Cont. • Let F(x)=F(X1,…Xn) be a logic function of n variables • If one of the inputs to the logic function, e.g. input Xi, is faulty, then the output would be F(X1…Xi…Xn). • The Boolean difference of F(X) with respect to Xi is defined as:
- 14. Cont. • The function dF(X)/dXi is called the Boolean difference of F(X) with respect to Xi • It is easy to see that when F(X1…Xi…Xn) is not equal to F(X1…Xi’…Xn), dF(X)/dXi = 1 and that when F(X1…Xi…Xn) is equal to F(X1…Xi’…Xn), dF(X)/dXi = 0 • the aim is to find input combinations for each fault occurring on Xi such that dF(X)/dXi = 1.
- 15. Cont. • Some useful properties of the Boolean difference are:
- 16. Example: • Consider the logic circuit shown in Fig. 3.3(a). Find the Boolean difference with respect to X3.
- 17. solution • This means that a fault on X3 will cause the output to be in error only if (X1X2)’X4, i.e. if X1 or X2 (or both) are equal to 0 and X4 equal to 1
- 18. Cont.
- 19. Example: • Find the partial Boolean difference associated with the path X2-l-n-p-F in the fig. below
- 20. Solution:
- 21. Cont. • The Boolean difference method generates all tests for every fault in a circuit. It is a complete algorithm and does not require any trial and error. However, the method is costly in terms of computation time and memory requirements.
- 22. Test Generation for Sequential Logic Circuits There two distinctly different approaches to the problem of finding tests for sequential circuits: 1. By converting a given synchronous sequential circuit into a one dimensional array of identical combinational circuits. Most techniques for generating tests for combinational circuits can then be applied. 2. By verifying whether or not a given circuit is operating in accordance with its state table
- 23. State Table Verification • In this approach a sequential machine is tested by performing an “experiment” on it, i.e. by applying an input signal and observing the output • Hence, the testing problem may be stated as follows: given the state table of a sequential machine, find an input/output sequence pair (X, Z) such that the response of the machine to X will be Z if and only if the machine is operating correctly
- 24. Checking experiment • Checking experiment: The application of input sequence X and the observation of the response, to see if it is Z. • Checking sequence: the sequence pair (X, Z) • Checking experiments are classified either as “adaptive” or “preset”. • In “adaptive” experiments the choice of the input symbols is based on the output symbols produced by a machine earlier in the experiment • In “preset” experiments the entire input sequence is completely specified in advance • . A measure of efficiency of an experiment is its “length”, which is the total number of input symbols applied to the machine during the execution of an experiment
- 25. The derivation of “checking sequence” • The derivation of “checking sequence” is based on the following assumptions: 1. The network is fully specified and deterministic. In a deterministic machine the next state is determined uniquely by the present state and the present input. 2. The network is strongly connected, i.e. for every pair of states qi and qj of the network, there exists an input sequence that takes the network from qi to qj. 3. The network in the presence of faults has no more states than those listed in its specification. In other words, no fault will increase the number of states.
- 26. Example: • Draw the successor tree for machine(m/c) M1 whose table is shown below Present state A B C D x=0 C,0 C,0 A,1 B,0 x=1 D,1 A,1 B,0 C,1
- 27. Successor tree
- 28. Homing experiment • Homing experiment: defines the final states • Homing sequence: ones and zeros that define the final states • Eg. For machine M1, 0,1 defines the final state sequence for final state: Initial state Response to 0,1 Final state A 0,1 B B 0,0 B C 1,1 D D 0,1 A
- 29. Homing tree • Homing tree: its a truncated version of the successor tree. • A node becomes a terminal if it has either: 1. The node is associated with an uncertainty vector whose non-homogenous components are associated with the same node at preceding levels 2. The node is associated with a trivial or homogenous vector
- 30. Distinguishing experiment • Distinguishing experiment: defines the initial state • Distinguishing sequence: ones and zeros that will lead to the initial states(from machine M1, 111 is a distinguishing sequence) sequence for M1 Initial state Response to 111 Final state A 110 B B 111 C C 011 D D 101 A
- 31. Distinguishing tree • Distinguishing tree: truncated version of successor tree • A node becomes a terminal if either: 1. The node is associated with an uncertainty vector whose non-homogenous components are associated with the same node at preceding levels 2. The node is associated with an uncertainty vector containing a homogenous non-trivial component 3. The node is associated with a trivial uncertainty vecor
- 32. Example: • For machine M2 shown below, find the shortest homing sequence and determine whether or not a distinguishing sequence exist and if any do exist, find the shortest one state table of machine M2 Present state A B C D inputs x=0 x=1 B,0 D,0 A,0 B,0 D,1 A,0 D,1 C,0
- 33. Solution (Successor tree)
- 34. Cont. • The shortest sequence is 010 Initial state Response to 010 Final state A 000 A B 001 D C 101 D D 101 D • The machine has no distinguishing sequence
- 35. Synchronizing experiment • It defines the final state regardless of the output or the initial state • Synchronizing sequence: ones and zeros that define the experiment • Eg. The synchronizing tree for machine M2
- 36. Synchronizing tree
- 37. Transfer sequence • It is the shortest input sequence that takes the machine from one state to another • Eg. T.S for machine M2 starting at B
- 38. Transfer tree • Shortest transfer sequence to take the machine from B to C is 011
- 39. Checking experiment (fault detection experiment) • For any strongly connected diagnosable experimental machine (diagnosable – has at least one distinguishing sequence), there are three steps in fault detection • Initialization phase: apply homing sequence followed by transfer sequence if necessary • State identification phase: apply distinguishing sequence to all different states • Transition verification phase: the machine is made to go through energy state transition, each state transition is checked by using distinguishing sequence
- 40. Fault tolerance design using error correcting codes 1. Hamming code 2. Horizontal and vertical parity schemes
- 41. Soft error correction using horizontal and vertical parity method • The method can correct all errors detectable by parity including multiple errors in a single word • Eg. Consider the five word memory shown below using odd parity.
- 42. Example: • • • • XOR all words 00111101 -(1) Assume word 3 bit 5 is in error XOR all words except word 3 10111110 -(2) XOR (1) and (2) to get the original word 1000001
- 43. Design for testability There are two approaches: 1. Testability design style 2. Testability measure analysis The use of testability design style guarantees that generating test for a circuit will not be impossible.
- 44. Testability measure analysis • This approach computes the difficulty of controlling and observing each internal node from primary input or outputs • The information is used in the design process to locate potential circuit testing problems and provide feedback about the effect of circuit modification on testability.
- 45. Design techniques • Adhoc technique: aim at a particular solution to a particular design problem. May involve data compression(signature analysis) • Structure technique: design methodology aim at generalized solution in testing problems. Eg. Level sensitivity scan design (LSSD), built-in logical block observer(BILBO). All allow testing of sequential circuits using only test patterns for the combinational portions of the circuit
- 46. Key concepts • Predictability: can the circuit be put in a known state from which all future states can be predicted? • Controllability: can the state of given node in a circuit be controlled from the primary input? • Observability: can the state of the network be determined from the primary inputs? In general, add some control gates and control lines to increase controllability and add output terminals for testing purposes (observability)
- 47. Reed-Muller expansion technique
- 48. Cont.
- 49. Example: • Given the function F(w,x,y)=wx+w’y+x’y’, find the Reed-Muller expansion and hence draw the circuit
- 50. Solution:
- 51. Cont. • Find the C’s Co = Fo = 1 C1=Fo+F4=0 C2=Fo+F2=1 C3=Fo+F1=0 C4=Fo+F2+F4+F6=1 C5=Fo+F1+F4+F5=1 C6=Fo+F1+F2+F3=1 C7=Fo+F1+F2+F3+F4+F5+F6+F7=0
- 52. Gookyi Agyemanh Nana Dennis (dennisgookyi@gmail.com)

No se han encontrado tableros de recortes públicos para esta diapositiva.

Parece que ya has recortado esta diapositiva en .

Crear un tablero de recortes

Sé el primero en comentar