Digital Control Systems

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CHAPTER (6)
Digital control systems
Objectives:
This chapter will consider digital control loops including Interfacing with digital
controller, analog to digital circuits, digital to analog circuits, and digital
controllers. After you have read this chapter, you should be able to
• Describe the digital control loop elements
• Compare between analog and digital control loops
• Describe A/D and D/A circuits
• Identify the major components of a PLC and describe their functions
• Read a basic ladder logic diagram and statement list
• Describe the operation of timers and counters

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6.1 Introduction to digital control systems
As computers have become more reliable and miniaturized, they have taken over the
controller function. Once analog controller is replaced by a digital one, we gain the following
advantages:
• Hardware is replaced by software, which is costly-effective
• Complex function can be implemented in software so easily rather then hardware
• Reliability in implementation, that means, you can simply modify the control function
in software without extra cost.
• Computers can be used in data logging (monitoring), supervisory control and can
control multiple loop simultaneously as the computers are well fast.
Digital controllers could take one of the forms:
• A computer or simply microprocessor board. Microprocessors are developed in the
early 1970s as a large scale integration of digital integrated circuits. Once they have
developed and started to be manufactured commercially, digital controller are
developed.
• Microcontroller is a microprocessor system on chip as a single integrated circuit. It
can be used in embedded control applications such as TV, mobile phones, Air
conditioner, Video Camera, Hard disk controllers, Robots, Smart car manufacturing,
...etc. It is a digital controller that can be used for a limited number of inputs and
outputs in process control applications.
• Programmable logic controller (PLCs). This type of controller can handle a very large
number (as hundreds or thousands) of digital inputs and outputs in industrial control
applications. It has a standard interfaces with the field measurements in the industry.
Therefore, it has increasing attention to replace old relay logic control cabinets in the
industry by PLC developments.
Figure 6.1 Digital control system
Set point
Analog signal
From the process
Digital word
n-bits
Digital word
n-bits
Process
DAC
ADC
Digital
controller
Analog input
to the process
Actuator
Measurement

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Digital control system consists of (see figure 6.1):
• Digital controller (computer, or microcontroller, or PLC)
• ADC, Analog to digital converter
• DAC, Digital to analog converter
Connecting digital circuitry to sensor devices is simple if the sensor devices are digital
inherently themselves. Switches, relays, and encoders are easily interfaced with gate circuits
due to the on/off nature of their signals. However, when analog devices are involved,
interfacing becomes much more complex. What is needed is a way to electronically translate
analog signals into digital (binary) quantities, and visa-versa. An analog-to-digital converter,
or ADC, performs the former task while a digital-to-analog converter, or DAC, performs the
latter. Error detection and controller action are determined by software. The digital controller
then provides output directly to the actuator via digital representation, which is converted to
the analog voltage by the DAC.
An ADC inputs an analog electrical signal such as voltage or current and outputs a binary
number. In block diagram form, it can be represented as such: A DAC, on the other hand,
inputs a binary number and outputs an analog voltage or current signal. Together, they are
often used in digital systems to provide complete interface with analog sensors and output
devices for control systems such as those used in automotive engine controls:
Figure 6.2 Computer control interface system
Since a digital controller is like a computer, it stores information in the form of ones and
zeros, referred to as binary digits (bits). Sometimes binary digits are used individually and
sometimes they are used to represent numerical values (See Appendix B to review the number
systems).

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6.2 Bases of ADC
The analog signal is a continuous representation of a signal, that it takes different values with
time. Digital signals have two values only or two level corresponding to logic 1 and logic zero
as shown in figure 6.3
Figure 6.3 ADC operations
The ADC requires three operations in sequence:
1- Sampling, we need to sample the analog signal at a constant rate. The sampler could
be an electronic switch. The critical question is how to select the sampling frequency.
2- Holding, that holds the sample in during the sampling period until a new sample is
captured. This is necessary to convert a constant value into digital word
3- ADC, it is often sequential circuit that takes a considerable time to convert the holding
sample into digital word. Different types of these circuits will be shown in section 6.4.
While, DAC requires two operations in sequence:
1- DAC, different circuits are given in section 6.3. DAC circuits are, generally, faster
than ADC ones and easier in implementation. Therefore, we will begin with DAC
circuitry and then move to ADC circuitry in the next sections.
2- Holding, it is very difficult to apply the discrete signal that outputs from DAC directly
to an analog process. It will excite the system and fatigue the actuator. Therefore,
holding these samples makes them in a continuous form (stepping levels).
6.2.1 Sampling and holding process
The basic concept of the sample and hold circuit is shown in figure
Figure 6.4 Sample and hold circuit S/H
Digital word
(n-bit)
Sample and hold
voltage
C
+
-FET
ADC
Analog input
signal
Voltage
follower

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The sample and hold is connected to the input of ADC. When the electronic switch (FET
transistor) is closed the capacitor voltage will track the input voltage. T some time, when a
conversion of the input signal is desired, the electronic switch is opened, isolating the
capacitor from the input signal. Thus, the capacitor will hold (be charged) to the voltage when
the switch was closed. The voltage follower allows this voltage to be impressed upon the
ADC input, but the capacitor does not discharge because of very high input impedance of the
follower. The start convert is then is then issued, and the conversion proceeds with the input
voltage remaining constant from the capacitor. When the conversion is complete the
electronic switch is reclosed to capture a new sample and the above sequence is repeated.
6.2.2 Selection of sampling frequency
When the sample period is too long (too slow), substantial details of the analog signal will be
missed. Notice how, especially in the latter portions of the analog signal, the digital output
utterly fails to reproduce the true shape. Even in the first section of the analog waveform, the
digital reproduction deviates substantially from the true shape of the wave. It is imperative
that an ADC's sample time is fast enough to capture essential changes in the analog
waveform. In data acquisition terminology, the highest-frequency waveform that an ADC can
theoretically capture is the so-called Nyquist frequency, equal to one-half of the ADC's sample
frequency. Therefore, if an ADC circuit has a sample frequency of 5000 Hz, the highest-
frequency waveform it can successfully resolve will be the Nyquist frequency of 2500 Hz. If
an ADC is subjected to an analog input signal whose frequency exceeds the Nyquist
frequency for that ADC, the converter will output a digitized signal of falsely low frequency.
This phenomenon is known as aliasing. Observe the following illustration to see how aliasing
occurs.
Figure 6.5 Aliasing Phenomenon
In the above figure, note how the period of the output waveform is much longer (slower) than
that of the input waveform, and how the two waveform shapes aren't even similar. Therefore,
to preserve the information of the input analog signal and to be able to recover it again, the
sampling frequency fs must verify the condition (Nyquist criterion)
fs > 2 fB (6.1)
The theoretical limit is fs=2fB, where fB is the frequency bandwidth of the controlled process.
In practice, a higher sampling frequency must be chosen as
fs = (6 to 25) fB (6.2)

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The following figure illustrates the effect of sampling frequency on the spectrum of sampled
signal.
Figure 6.6 Spectrum of sampled signal
In the above figure, we have two cases for the same process that have a frequency bandwidth
fB. Case1 corresponds to a good selection of the sampling frequency using equation 6.1, while
case 2 corresponds to appearance of distortions (overlapping phenomenon of aliasing). In
order to avoid the folding (aliasing) of the spectrum and thus of the distortions, the analog
measurement signals must be filtered prior to sampling to eliminate high noise frequencies.
Remarks
1- Frequency bandwidth for first order system is fB=1/(2π τ), where τ is the time constant
2- The system bandwidth frequency is not the only limit to select the sampling
frequency, there is also other constraints due to time consideration in ADC, DAC, and
microprocessor that executes the control program. In general, the sampling period has
to be large enough for timing consideration and also to respect the condition in
equation (6.1) to avoid aliasing effect. Finally, the sampling period Ts can be
computed using the following equation
1/(2 fB) > Ts > (TADC + Tµp +TDAC) (6.3)
Where TADC = conversion time of Analog to digital converter
TDAC = conversion time of digital to analog converter (very small)
Tµp = Execution time of the control program in microprocessor, it
depends the speed of microprocessor
Example: Consider a second order system with wo=1 (natural frequency) and ζ=0.7 (damping
factor). Calculate the sampling frequency.
Solution
It is clear that the bandwidth frequency fB is fB= (wo/2π) Hz
The practical rule to choose the sampling frequency fs is different than the theoretical limit in
equation (6.1), it can be chosen according to fs = (6 to 25) fB ≈ 10 fB = (10/2π) Hz
fs 2fs 3fs
fs 2fs 3fs
Case 1: fs > 2 fB
Case 2:
fs < 2 fB (Aliasing)

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6.3 Digital to Analog Circuits (DAC)
6.3.1 The R/2n
R DAC
This DAC circuit, otherwise known as the binary-weighted-input DAC, is a variation on the
inverting summer op-amp circuit. If you recall, the classic inverting summer circuit is an
operational amplifier using negative feedback for controlled gain, with several voltage inputs
and one voltage output. The output voltage is the inverted (opposite polarity) sum of all input
voltages:
Figure 6.7 R/2n
R DAC
For a simple inverting summer circuit, all resistors must be of equal value. If any of the input
resistors were different, the input voltages would have different degrees of effect on the
output, and the output voltage would not be a true sum. Let's consider, however, intentionally
setting the input resistors at different values. Suppose we were to set the input resistor values
at multiple powers of two: R, 2R, and 4R, instead of all the same value R.
Starting from V1 and going through V3, this would give each input voltage exactly half the
effect on the output as the voltage before it. In other words, input voltage V1 has a 1:1 effect
on the output voltage (gain of 1), while input voltage V2 has half that much effect on the
output (a gain of 1/2), and V3 half of that (a gain of 1/4). These ratios are not arbitrarily
chosen: they are the same ratios corresponding to place weights in the binary numeration
system. If we drive the inputs of this circuit with digital gates so that each input is either 0
volts or full supply voltage, the output voltage will be an analog representation of the binary
value of these three bits.
Figure 6.8 weighted resistors DAC

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If we chart the output voltages for all eight combinations of binary bits (000 through 111)
input to this circuit, we will get the following progression of voltages:
Table 6.1 Three-bit DAC output
Binary Output Voltage
000 0.00 V
001 -1.25 V
010 -2.5 V
011 -3.75 V
100 -5 V
101 -6.25 V
110 -7.5 V
111 -8.75 V
Note that with each step in the binary count sequence, there results a 1.25 volt change in the
output. If we wish to expand the resolution of this DAC (add more bits to the input), all we
need to do is add more input resistors, holding to the same power-of-two sequence of values:
Figure 6.9 Weighted resistors 6-bit DAC
It should be noted that all logic gates must output exactly the same voltages when in the
"high" state. If one gate is outputting +5.02 volts for a "high" while another is outputting only
+4.86 volts, the analog output of the DAC will be adversely affected. Likewise, all "low"
voltage levels should be identical between gates, ideally 0.00 volts exactly. It is recommended
that CMOS output gates are used, and that input/feedback resistor values are chosen so as to
minimize the amount of current each gate has to source or sink.

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6.3.2 The R-2R DAC
An alternative to the binary-weighted-input DAC is the so-called R/2R DAC, which uses
fewer unique resistor values. A disadvantage of the former DAC design was its requirement
of several different precise input resistor values: one unique value per binary input bit. There
is, however, a more efficient design methodology. By constructing a different kind of resistor
network on the input of our summing circuit, we can achieve the same kind of binary
weighting with only two kinds of resistor values, and with only a modest increase in resistor
count. This "ladder" network looks like this:
Figure 6.10 R-2R DAC
Mathematically analyzing this ladder network is a bit more complex than for the previous
circuit, where each input resistor provided an easily-calculated gain for that bit. To find the
input-output relationship of this circuit, you can apply Thevenin's theorem for each binary
input (remember to consider the effects of the virtual ground), then apply the superposition
theorem (output is equal to the sum of all individual response of each bit) to obtain the global
response of the circuit. Finally, you should obtain the same table as in weighted resistor case
(see table 6.1). As was the case with the binary-weighted DAC design, we can modify the
value of the feedback resistor to obtain any "span" desired. For example, if we're using +5
volts for a "high" voltage level and 0 volts for a "low" voltage level, we can obtain an analog
output directly corresponding to the binary input (011 = -3 volts, 101 = -5 volts, 111 = -7
volts, etc.) by using a feedback resistance with a value of 1.6R instead of 2R.
In general, the output of the DAC can be defined as a scaling of some reference voltage where
each digital input is either VR volt (logic one) or 0 volt (logic 0). Therefore, the output is
given by:
[ ]-n
n
-2
2
-1
1Rout 2b...2b2bVV +++=
(6.4)
Where Vout = analog voltage output
VR = Reference voltage
b1, b2, …,bn = n-bit binary word in 1's and 0's
b1 is the MSB
bn is the LSB
Note that, the smallest possible change ∆Vout in the analog output is simply given by

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-n
Rout 2VV =∆
(6.5)
For any given number in decimal N equivalent to a digital word, we find the output as






= nRout
2
N
VV
(6.6)
Example
Determine the number of bits a DAC converter must have to provide output increments of
0.04 volts or less. The reference is 10 volts.
Solution
By solving the following equation, the number of required bits n can be determined
∆Vout =0.04 =10 (2-n
)
log (0.04) = log 10 – n log 2
n= (log 10 – log 0.04)/log 2
n= 7.966
Thus, n= 8 bits will be satisfactory. This can be verified by calculating again the smallest
output variation
∆Vout =10 (2-8
) = 0.0390625 volts
Example
What is the output voltage of a 10-bit ADC with a 10 volt reference if the input is
a) (0010110101)2=0B5H
b) 20FH
What input is needed to get a 6.5 volt output?
Solution
a) using equation 6.4
Vout = 10[2-3
+ 2-5
+ 2-6
+ 2-8
+ 2-10
]= 10[0.1767578]=1.767578 volts
b) we have 20FH=52710 and 210
=1024, so
Vout = (527/1024) 10 = 5.14648 volts
c) using equation 6.6
N= 1024 (6.5/10) = 665.6 ≈ 666 = 29AH in hexadecimal

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6.4 Analog to Digital Circuits (ADC)
6.4.1 Digital ramp ADC
Also known as the stair-step ramp, or simply counter A/D converter, this is also fairly easy to
understand but unfortunately suffers from several limitations. The basic idea is to connect the
output of a free-running binary counter to the input of a DAC, then compare the analog output
of the DAC with the analog input signal to be digitized and use the comparator's output to tell
the counter when to stop counting and reset. The following schematic shows the basic idea:
Figure 6.11 Digital ramp ADC
As the counter counts up with each clock pulse, the DAC outputs a slightly higher (more
positive) voltage Vo. This voltage is compared against the input voltage Vin by the
comparator. If the input voltage is greater than the DAC output, the comparator's output will
be high (flag = logic 1 as digital output) and the counter will continue counting normally.
Eventually, though, the DAC output will exceed the input voltage, causing the comparator's
output to go low (flag = logic zero as digital output). This will cause two things to happen:
first, the high-to-low transition of the comparator's output will cause the shift register to
"load" whatever binary count is being output by the counter, thus updating the ADC circuit's
output; secondly, the counter will receive a low signal on the active-low LOAD input, causing
it to reset to 00000000 on the next clock pulse. The effect of this circuit is to produce a DAC
output that ramps up to whatever level the analog input signal is at, output the binary number
corresponding to that level, and start over again.
The fact that the circuit's need to count all the way from 0 at the beginning of each count
cycle makes for relatively slow sampling of the analog signal, places the digital-ramp ADC at
a disadvantage to other counter strategies. Notice that the maximum allowed count rate is
determined by the sum of the DAC settling time tdA , the comparator settling time tcom, and
the logic reaction time tL. The latter is usually negligible at all but the ultimate speeds. The
converter is obviously slow, taking a maximum of 2n
clock cycles to convert to n bits. The n
conversion time is also variable - which can be a disadvantage. The maximum conversion rate
is given by:
LcomdA
max
ttt
1
f
++
= (6.7)

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6.4.2 Successive approximation ADC
This circuit uses a very special counter known as a successive-approximation register (SAR).
This register counts by trying all values of bits starting with the MSB and finishing at the
LSB, instead of counting up in binary sequence. Throughout the count process, the register
monitors the comparator's output to see if the binary count is less than or greater than the
analog signal input, adjusting the bit values accordingly to 1 or 0 value. The way the register
counts is identical to the "trial-and-fit" method of decimal-to-binary conversion, whereby
different values of bits are tried from MSB to LSB to get a binary number that equals the
original decimal number. The advantage to this counting strategy is much faster than the
previous circuit of digital ramp ASC. Without showing the inner workings of the successive-
approximation register (SAR), the circuit looks like this:
Figure 6.12 Successive approximation ADC
The advantage of this process is that it produces a result in a defined length of time, n cycles
for an n-bit converter, and that this time is much smaller than the counting algorithm since
2n
>> n. The disadvantage is that if the value to be measured changes during the measurement
period, then the result can be wrong. "Successive approximation" converters are by far the
most popular converters for microprocessors in circumstances where a small number of bits
of accuracy are required (small # 14). For larger numbers of bits a number of factors combine
to make other solutions more attractive.
Example: Consider a 4 bit-converter, Vref= 10 V, and the Vin = 7 volt. Find the equivalent
binary code using successive approximation technique.
Solution
In 1st
clock period, start with the code 1000 that equivalent to DAC of 5V. The comparator
output will be 1, that means, the decision is to set this bit, the code is1000.
In 2nd
clock period, set next bit to 1, that means, the code to be tested is 1100, which is
equivalent to 7.5 volt, the comparator output will be 0, that means, the decision is to reset this
bit, the code is 1000.
In 3rd
equivalent to 8.75 volt, the comparator output will be 0, that means, the decision is to reset
this bit, the code is 1000.
In 4th
equivalent to 6.875 volt, the comparator output will be 1, that means, the decision is to set this
bit, the code is 1001. This is final code after four clock pulses (conversion time) is 1001.

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6.4.3 Tracking ADC
Instead of a regular "up" counter driving the DAC, this circuit uses an up/down counter. The
counter is continuously clocked, and the up/down control line is driven by the output of the
comparator. So, when the analog input signal exceeds the DAC output, the counter goes into
the "count up" mode. When the DAC output exceeds the analog input, the counter switches
into the "count down" mode. Either way, the DAC output always counts in the proper
direction to track the input signal.
Figure 6.13 Tracking ADC
Notice how no shift register is needed to buffer the binary count at the end of a cycle. Since
the counter's output continuously tracks the input (rather than counting to meet the input and
then resetting back to zero), the binary output is updated with every clock pulse. An
advantage of this converter circuit is speed, since the counter never has to reset.
Note the much faster update time than any of the other "counting" ADC circuits. Also note
how at the very beginning of the plot where the counter had to "catch up" with the analog
signal, the rate of change for the output was identical to that of the first counting ADC. Also,
with no shift register in this circuit, the binary output would actually ramp up rather than jump
from zero to an accurate count as it did with the counter and successive approximation ADC
circuits. Perhaps the greatest drawback to this ADC design is the fact that the binary output is
never stable: it always switches between counts with every clock pulse, even with a perfectly
stable analog input signal. This phenomenon is informally known as bit bobble, and it can be
problematic in some digital systems. This tendency can be overcome, though, through the
creative use of a shift register. For example, the counter's output may be latched through a
parallel-in/parallel-out shift register only when the output changes by two or more steps.
Building a circuit to detect two or more successive counts in the same direction takes a little
ingenuity, but is worth the effort.

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6.4.4 Dual-Slope ADC
It is possible to avoid using a DAC if we substitute an analog ramping circuit and a digital
counter with precise timing. This is the basic idea behind the so-called integrating ADC.
Consider the following circuit, in operation the integrator is first zeroed (close SW2 for short
time), then attached to the input (SW1 up) for a fixed time M counts of the clock (frequency
1/t). At the end of that time it is attached to the reference voltage (SW1 down), a digital
counter has start to count (start of conversion), and the number of counts N which accumulate
before the integrator reaches zero volts output and the comparator output changes are
determined to signal to the logic circuit that is not shown in the figure, that end of conversion
is reached.
Figure 6.14 Dual-Slope ADC
Figure 6.15 Timing diagram of Dual-Slope ADC
The equations of operation are therefore:
(N/M)VV
RC
(Nt)V
RC
(Mt)V
V
refin
refin
x
=
==
(6.8)
The unknown voltage is then just Vref (N/M) and is reasonably independent of everything
else. The main problem with a simple dual slope ADC is in returning the converter to an exact
zero before the start of each conversion as interpreted by an imperfect comparator.

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6.4.5 Voltage-to-Frequency ADC
The voltage-to-frequency converter uses a linear voltage controlled oscillator to produce a
frequency output.
Figure 6.16 Voltage to frequency ADC
Consider a simple integrating system with a switched current source as shown here. If every
time the comparator "flips" we switch on the current source I for a time t and drain a charge
(It) from the capacitor, the total charge collected in a time T is given by:
tINT
R
V
dt
R
V
Q in
T
0
in
=== ∫
(6.9)
Where N = number of discharges in the integration time T
inV = average voltage input
The average frequency is therefore,
inin VV
RIt
1
T
N
f ∝





== (6.10)
Therefore, we can easily recover the voltage by counting the output of the system for a fixed
time T as shown in figure.
Figure 6.17 Counting a simple V-f output
V-f converters are normally limited in output frequency to about 100kHz which imposes a
limit of 1:105
in resolution (0.001%) for a one second measurement which is still
inconveniently long.

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6.4.6 Delta-Sigma (∆Σ) ADC
One of the more advanced ADC technologies is the so-called delta-sigma, or ∆Σ (using the
proper Greek letter notation). In mathematics and physics, the capital Greek letter delta (∆)
represents difference or change, while the capital letter sigma (Σ) represents summation: the
adding of multiple terms together. Sometimes this converter is referred to by the same Greek
letters in reverse order: sigma-delta, or Σ∆. In a ∆Σ converter, the analog input voltage signal
is connected to the input of an integrator, producing a voltage rate-of-change, or slope, at the
output corresponding to input magnitude. This ramping voltage is then compared against
ground potential (0 volts) by a comparator. The comparator acts as a sort of 1-bit ADC,
producing 1 bit of output ("high" or "low") depending on whether the integrator output is
positive or negative. The comparator's output is then latched through a D-type flip-flop
clocked at a high frequency, and fed back to another input channel on the integrator, to drive
the integrator in the direction of a 0 volt output. The basic circuit looks like this:
Figure 6.18 Delta-Sigma (∆Σ) ADC
The leftmost op-amp is the (summing) integrator. The next op-amp the integrator feeds into is
the comparator, or 1-bit ADC. Next, the D-type flip-flop comes, which latches the
comparator's output at every clock pulse, sending either a "high" or "low" signal to the next
comparator at the top of the circuit. This final comparator is necessary to convert the single-
polarity 0V / 5V logic level output voltage of the flip-flop into a +V / -V voltage signal to be
fed back to the integrator. If the integrator output is positive, the first comparator will output a
"high" signal to the D input of the flip-flop. At the next clock pulse, this "high" signal will be
output from the Q line into the non-inverting input of the last comparator. This last
comparator, seeing an input voltage greater than the threshold voltage of 1/2 +V, saturates in
a positive direction, sending a full +V signal to the other input of the integrator. This +V
feedback signal tends to drive the integrator output in a negative direction. If that output
voltage ever becomes negative, the feedback loop will send a corrective signal (-V) back
around to the top input of the integrator to drive it in a positive direction. This is the delta-
sigma concept in action: the first comparator senses a difference (∆) between the integrator
output and zero volts. The integrator sums (Σ) the comparator's output with the analog input
signal. Functionally, this results in a serial stream of bits output by the flip-flop. If the analog
input is zero volts, the integrator will have no tendency to ramp either positive or negative,
except in response to the feedback voltage. In this scenario, the flip-flop output will

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continually oscillate between "high" and "low," as the feedback system "hunts" back and
forth, trying to maintain the integrator output at zero volts:
Figure 6.19 Delta-Sigma (∆Σ) ADC with zero voltage input
By applying a negative analog input signal to the integrator, we force its output to ramp more
steeply in the positive direction. Thus, the feedback system has to output more 1's to bring the
integrator output back to zero volts as shown in figure.
Figure 6.20 Delta-Sigma (∆Σ) ADC with negative voltage input
By applying a positive analog input signal to the integrator, we force its output to ramp more
steeply in the negative direction. Thus, the feedback system has to output more 0's to bring the
integrator output back to zero volts. A parallel binary number output can be obtained from
this circuit by averaging the serial stream of bits together. For example, a counter circuit
could be designed to collect the total number of 1's output by the flip-flop in a given number
of clock pulses. This count would then be indicative of the analog input voltage.

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6.4.7 Flash ADC
Every converter has its advantages – and the flash converter, converts in a flash, i.e. very fast.
It is a brother to the successive approximation converter but whereas the successive
approximation converter compares to a "guess" each time, the flash converter compares to all
guesses simultaneously and then decides the "best" value from the results. Note that a flash
converter is very extravagant in hardware - but if you have to convert at 10 M samples/Sec
you have to give up something! The following figure illustrates a 3-bit flash ADC circuit.
Figure 6.21 Flash ADC
Also called the parallel A/D converter, this circuit is the simplest to understand. It is formed
of a series of comparators, each one comparing the input signal to a unique reference voltage.
The comparator outputs connect to the inputs of a priority encoder circuit, which then
produces a binary output. Vref is a stable reference voltage provided by a precision voltage
regulator as part of the converter circuit, not shown in the schematic. As the analog input
voltage exceeds the reference voltage at each comparator, the comparator outputs will
sequentially saturate to a high state. The priority encoder generates a binary number based on
the highest-order active input, ignoring all other active inputs.
Not only is the flash converter the simplest in terms of operational theory, but it is the most
efficient of the ADC technologies in terms of speed, being limited only in comparator and
gate propagation delays. Unfortunately, it is the most component-intensive for any given
number of output bits. This three-bit flash ADC requires eight comparators. A four-bit version
would require 16 comparators. With each additional output bit, the number of required
comparators doubles. Considering that eight bits is generally considered the minimum
necessary for any practical ADC (256 comparators needed!), the flash methodology quickly
shows its weakness in term of number of components. An additional advantage of the flash
converter, often overlooked, is the ability for it to produce a non-linear output. With equal-
value resistors in the reference voltage divider network, each successive binary count
represents the same amount of analog signal increase, providing a proportional response. For
special applications, however, the resistor values in the divider network may be made non-
equal. This gives the ADC a custom, nonlinear response to the analog input signal. No other
ADC design is able to grant this signal-conditioning behavior with just a few component
value changes.

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6.5 Practical considerations of ADC circuits
Perhaps the most important consideration of an ADC is its resolution. Resolution is the
number of binary bits output by the converter. Because ADC circuits take in an analog signal,
which is continuously variable, and resolve it into one of many discrete steps, it is important
to know how many of these steps there are in total.
For example, an ADC with a 10-bit output can represent up to 1024 (210
) unique conditions of
signal measurement. Over the range of measurement from 0% to 100%, there will be exactly
1024 unique binary numbers output by the converter (from 0000000000 to 1111111111,
inclusive). An 11-bit ADC will have twice as many states to its output (2048, or 211
),
representing twice as many unique conditions of signal measurement between 0% and 100%.
Resolution is very important in data acquisition systems (circuits designed to interpret and
record physical measurements in electronic form).
Example:
Suppose we were measuring the height of water in a 40-foot tall storage tank using an
instrument with a 10-bit ADC. 0 feet of water in the tank corresponds to 0% of measurement,
while 40 feet of water in the tank corresponds to 100% of measurement. Because the ADC is
fixed at 10 bits of binary data output, it will interpret any given tank level as one out of 1024
possible states. To determine how much physical water level will be represented in each step
of the ADC, we need to divide the 40 feet of measurement span by the number of steps in the
0-to-1024 range of possibilities, which is 1023 (one less than 1024). Doing this, we obtain a
figure of 0.039101 feet per step. This equates to 0.46921 inches per step, a little less than half
an inch of water level represented for every binary count of the ADC.
Figure 6.22 Digital measurement of a tank level
This step value of 0.039101 feet (0.46921 inches) represents the smallest amount of tank level
change detectable by the instrument. Admittedly, this is a small amount, less than 0.1% of the
overall measurement span of 40 feet. However, for some applications it may not be fine
enough. Suppose we needed this instrument to be able to indicate tank level changes down to

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one-tenth of an inch. In order to achieve this degree of resolution and still maintain a
measurement span of 40 feet, we would need an instrument with more than ten ADC bits.
To determine how many ADC bits are necessary, we need to first determine how many 1/10
inch steps there are in 40 feet. The answer to this is 40/(0.1/12), or 4800 steps of 1/10 inch
step in 40 feet. Thus, we need enough bits to provide at least 4800 discrete steps in a binary
counting sequence. 10 bits gave us 1023 steps, and we knew this by calculating 2 to the power
of 10 (210
= 1024) and then subtracting one. Following the same mathematical procedure, we
have (211
-1 = 2047, 212
-1 = 4095, and 213
-1 = 8191). 12 bits falls shy of the amount needed
for 4800 steps, while 13 bits is more than enough. Therefore, we need an instrument with at
least 13 bits of resolution.
Another important consideration of ADC circuitry is its sample frequency, or conversion rate.
This is simply the speed at which the converter outputs a new binary number. Like resolution,
this consideration is linked to the specific application of the ADC. If the converter is being
used to measure slow-changing signals such as level in a water storage tank, it could probably
have a very slow sample frequency and still perform adequately. Conversely, if it is being
used to digitize an audio frequency signal cycling at several thousand times per second, the
converter needs to be considerably faster.
Yet another measure of ADC performance is something called step recovery. This is a
measure of how quickly an ADC changes its output to match a large, sudden change in the
analog input. In some converter technologies especially, step recovery is a serious limitation.
One example is the tracking converter, which has a typically fast update period but a
disproportionately slow step recovery. An ideal ADC has a great many bits for very fine
resolution, samples at lightning-fast speeds, and recovers from steps instantly. It also,
unfortunately, doesn't exist in the real world. Of course, any of these traits may be improved
through additional circuit complexity, either in terms of increased component count and/or
special circuit designs made to run at higher clock speeds. Different ADC technologies,
though, have different strengths. Here is a summary of them ranked from best to worst:
Resolution/complexity ratio: Single-slope integrating, dual-slope integrating, counter,
tracking, successive approximation, and flash.
Speed: Flash, tracking, successive approximation, single-slope integrating & counter, and
dual-slope integrating.
Step recovery: Flash, successive-approximation, single-slope integrating & counter, dual-
slope integrating, and tracking. The following figure presents a summary for ADC
performance.
Figure 6.23 Performance of ADC types

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6.6 Programmable Logic Controllers
Many manufacturing operations are ON/OFF in nature, that is a conveyor or heaters is either
on or off, a valve is either open or closed, and so on. In the past, these types of discrete
control functions were often provided by a system of electrical relays wired according to a
complex diagram into what was called a relay logic system. In recent years, computers have
also taken over the operation of such relay logic controllers, known as programmable logic
controllers (PLCs). Even though originally designed to control discrete state (ON/OFF)
systems, they are capable also to control analog control loops. A PLC monitors inputs, makes
decisions based on its program, and controls outputs to automate a process or machine as
shown in figure. This section is meant to supply the reader with basic information on the
functions and configurations of PLCs.
Figure 6.24 PLC operation environment
6.6.1 Fundamental elements in a PLC
Typically a PLC system has five basic elements:
• Input modules: 5 V, 24 V, 110 V, 240 V
• Output modules: relay type (ac and dc switching), transistor type (dc switching), or
triac type (loads with ac power supply)
• Central processing module (CPU) + memory
• Power supply module
• Programming device
• Operator interface (optional)
Figure 6.25 PLC elements

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The input module accepts a variety of digital or analog signals from various field devices
(sensors) and converts them into a logic signal that can be used by the CPU. The CPU module
makes decisions and executes control instructions based on program instructions in memory.
Output modules convert control instructions from the CPU into a digital or analog signal that
can be used to control various field devices (actuators). A power supply module is needed to
convert the main a.c. voltage to necessary voltage level for the processor and the circuits in
the input and output modules. A programming device is used to input the desired instructions
in the memory of the processor. These instructions determine what the PLC will do for a
specific input. An operator interface device allows process information to be displayed and
new control parameters to be entered. This module is optional and may be not found in some
applications.
Input/output channels provide signal conditioning and isolation functions so that sensors and
actuators can often be directly connected to them without the need for other circuitry.
Electrical isolation from the external world is usually by means of optoisolators (the term
optocoupler is also often used).
There are two common types of mechanical design:
• Single box or board type, it is commonly used for small programmable controllers and
is supplied as an integral compact package complete with power supply, processor,
memory, and input/output units. Typically such a PLC might have 40 input/output
points.
• Modular and Rack types, it is commonly used a large number of input/output points.
The modular type consists of separate modules for power supply, processor, memory,
and input/output units. These modules are often mounted on rails within a metal
cabinet. The rack type can be used for all sizes of programmable controllers and has
the various functional modules packaged in individual modules which can be
plugged into sockets in a base rack.
(a) Single box type (b) Modular type
Figure 6.26 PLC Configurations
Examples of functional modules for modular and rack type are:
• Extension memory module to be used for large program applications.
• Communication module to communicate between different PLCs in network
applications.
• PID module to control a fast analog input/output control loops
• High speed counter module for specific applications
Since a PLC is a computer, it stores information in the form of On or Off conditions (1 or 0),
referred to as binary digits (bits). Sometimes binary digits are used individually and
sometimes they are used to represent numerical values. Various number systems are used by
PLCs (See Appendix B to review the number systems).

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Simple PLC example: Pushbuttons (sensors), in this following figure, connected to PLC
inputs, can be used to start and stop a motor connected to a PLC through a motor starter
(actuator to deliver high electrical power).
Figure 6.27 Application example
Prior to PLCs, many of these control tasks were solved with contactor or relay controls. This
is often referred to as hardwired control. Circuit diagrams had to be designed, electrical
components specified and installed, and wiring lists created. Electricians would then wire the
components necessary to perform a specific task. If an error was made, the wires had to be
reconnected correctly. A change in function or system expansion required extensive
component changes and rewiring. The same, as well as more complex tasks can be done with
a PLC. Wiring between devices and relay contacts is done in the PLC program. Hard-wiring,
though still required to connect field devices, is less intensive. Modifying the application and
correcting errors are easier to handle. It is easier to create and change a program in a PLC than
it is to wire and rewire a circuit. Following are just a few of the advantages of PLCs:
• Smaller physical size than hard-wire solutions
• Easier and faster to make changes (reliability of software)
• PLCs have integrated diagnostics and override functions
• Diagnostics are centrally available
• Applications can be immediately documented
• Applications can be duplicated faster and less expensively
6.6.2 PLC terminology
The language of PLCs consists of a commonly used set of terms; many of which are unique to
PLCs. In order to understand the ideas and concepts of PLCs, an understanding of these terms
is necessary.
Sensor
A sensor is a device that converts a physical condition into an electrical signal for use by the
PLC. Sensors are connected to the input of a PLC. A pushbutton is one example of a sensor
that is connected to the PLC input. An electrical signal is sent from the pushbutton to the PLC
indicating the condition (open/closed) of the pushbutton contacts.

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Figure 6.28 Pushbutton input to PLC
Actuators
Actuators convert an electrical signal from the PLC into a physical condition. Actuators are
connected to the PLC output. A motor starter is one example of an actuator that is connected
to the PLC output. Depending on the output PLC signal the motor starter will either start or
stop the motor.
Figure 6.29 Motor starter signal from PLC
Discrete input
A discrete (digital) input is an input that is either in an ON or OFF condition. Pushbuttons,
toggle switches, limit switches, proximity switches, and contact closures are examples of
discrete sensors which are connected to the PLCs discrete or digital inputs. In the ON
condition a discrete input may be referred to as logic 1 or logic high. In the OFF condition a
discrete input may be referred to as logic 0 or logic low.
Figure 6.30 Discrete inputs to PLC
A Normally Open (NO) pushbutton has a one side of the pushbutton is connected to the first
PLC input. The other side of the pushbutton is connected to a 24 VDC power supply. In the
open state, no voltage is present at the PLC input (OFF condition). When the pushbutton is
depressed (closed), 24 VDC is applied to the PLC input (ON condition).

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Analog Inputs
An analog input is an input signal that has a continuous signal. Typical analog inputs may
vary from 4 to 20 milliamps, or 0 to 10 volts. In the following example, a level transmitter
monitors the level of liquid in a tank. Depending on the level transmitter, the signal to the
PLC can either increase or decrease as the level increases or decreases.
Figure 6.31 Analog level measurement to PLC
Discrete Outputs
A discrete output is an output that is either in an ON or OFF condition. Solenoids, contactor
coils, and lamps are examples of actuator devices connected to discrete outputs. Discrete
outputs may also be referred to as digital outputs. In the following example, a lamp can be
turned on or off by the PLC output it is connected to.
Figure 6.32 Discrete output from PLC
Analog Outputs
An analog output is an output signal that has a continuous signal. The output may be as
simple as a 0-10 VDC level that drives an analog meter. Examples of analog meter outputs
are speed, weight, and temperature. The output signal may also be used on more complex
applications such as a current-to pneumatic transducer that controls an air-operated flow-
control valve.
Figure 6.33 Analog output from PLC

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CPU
The central processor unit (CPU) is a microprocessor system that contains the system memory
and is the PLC decision making unit. The CPU monitors the inputs and makes decisions based
on instructions held in the program memory. The CPU performs relay, counting, timing, data
comparison, and sequential operations.
Figure 6.34 CPU of a PLC
Programming
A program consists of one or more instructions that accomplish a task. Programming a PLC is
simply constructing a set of instructions. There are several ways to look at a program such as
ladder logic, statement lists, or function block diagrams.
Ladder Logic Diagram
Ladder logic (LAD) is one programming language used with PLCs. Ladder logic uses
components that resemble elements used in a line diagram format to describe hard-wired
control. The left vertical line of a ladder logic diagram represents the power or energized
conductor. The output element or instruction represents the neutral or return path of the
circuit. The right vertical line, which represents the return path on a hard-wired control line
diagram, is omitted. Ladder logic diagrams are read from left-to-right, top-to-bottom. Rungs
are sometimes referred to as networks. A network may have several control elements, but only
one output coil.
Figure 6.35 Ladder logic diagram example
In the example shown above I0.0, I0.1 and Q0.0 represent the first instruction combination. If
inputs I0.0 and I0.1 are energized, output relay Q0.0 energizes. The inputs could be switches,
pushbuttons, or contact closures. I0.4, I0.5, and Q1.1 represent the second instruction
combination. If either input I0.4 or I0.5 is energized, output relay Q0.1 energizes.

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Statement list
A statement list (STL) provides another view of a set of instructions. The operation, what is to
be done, is shown on the left. The operand, the item to be operated on by the operation, is
shown on the right. A comparison between the statement list shown below, and the ladder
logic shown on the previous page, reveals a similar structure. The set of instructions in this
statement list perform the same task as the ladder diagram.
Figure 6.36 Statement list
Function Block Diagram
Function Block Diagram (FBD) provides another view of a set of instructions. Each function
has a name to designate its specific task. Functions are indicated by a rectangle. Inputs are
shown on the left-hand side of the rectangle and outputs are shown on the right-hand side.
The function block diagram shown below performs the same function as shown by the ladder
diagram and statement list.
Figure 6.37 Functional block diagram
PLC Scan
The PLC program is executed as part of a repetitive process referred to as a scan. A PLC scan
starts with the CPU reading the status of inputs. The application program is executed using
the status of the inputs. Once the program is completed, the CPU performs internal
diagnostics and communication tasks. The scan cycle ends by updating the outputs and then
starts over. The cycle time depends on the size of the program, the number of I/Os, and the
amount of communication required.

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Software
Software is any information in a form that a computer or PLC can use. Software includes the
instructions or programs that direct hardware.
Hardware
Hardware is the actual equipment. The PLC, the programming device, and the connecting
cable are examples of hardware.
Memory Size
Kilo, abbreviated K, normally refers to 1000 units. When talking about computer or PLC
memory, however, 1K means 1024. This is because of the binary number system (210
=1024).
This can be 1024 bits, 1024 bytes, or 1024 words, depending on memory type.
RAM
Random Access Memory (RAM) is memory where data can be directly accessed at any
address. Data can be written to and read from RAM. RAM is used as a temporary storage
area. RAM is volatile, meaning that the data stored in RAM will be lost if power is lost. A
battery backup is required to avoid losing data in the event of a power loss.
ROM
Read Only Memory (ROM) is a type of memory that data can be read from but not written to.
This type of memory is used to protect data or programs from accidental erasure. ROM
memory is nonvolatile. This means a user program will not lose data during a loss of
electrical power. ROM is normally used to store the programs that define the capabilities of
the PLC.
EPROM
Erasable Programmable Read Only Memory (EPROM) provides some level of security
against unauthorized or unwanted changes in a program. EPROMs are designed so that data
stored in them can be read, but not easily altered. Changing EPROM data requires a special
effort. UVEPROMs (ultraviolet erasable programmable read only memory) can only be
erased with an ultraviolet light. EEPROM (electronically erasable programmable read only
memory), can only be erased electronically.
Firmware
Firmware is user or application specific software burned into EPROM and delivered as part of
the hardware. Firmware gives the PLC its basic functionality.
Figure 6.38 PLC programming using PC via serial interface

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In order to create or change a program, the following items are needed:
• PLC
• Programming Device
• Programming Software
• Connector Cable
Programming Devices
The program is created using a special programming device and then transferred to the PLC
via a communication cable. This device uses dedicated software for application development.
A personal computer (PC) or lab-top, with the dedicated software for application
development, can also be used as a programming device. The programming software can be
run Off-line or On-line. Offline programming allows the user to edit the ladder diagram and
perform a number of maintenance tasks. The PLC does not need to be connected to the
programming device in this mode. On-line programming requires the PLC to be connected to
the programming device. In this mode program changes are downloaded to the PLC. In
addition, status of the input/output elements can be monitored. The CPU can be started,
stopped, or reset.
Forcing
Forcing is another useful tool in the commissioning of an application. It can be used to
temporarily override the input or output status of the application in order to test and debug the
program. The force function can also be used to override discrete output points. The force
function can be used to skip portions of a program by enabling a jump instruction with a
forced memory bit.
6.6.3 Programming a PLC
In order to understand the instructions a PLC is to carry out, an understanding of the language
is necessary. The language of PLC ladder logic consists of a commonly used set of symbols
that represent control components and instructions as following.
Contacts
One of the most confusing aspects of PLC programming for first-time users is the relationship
between the device that controls a status bit and the programming function that uses a status
bit. Two of the most common programming functions are the normally open (NO) contact and
the normally closed (NC) contact. Symbolically, power flows through these contacts when
they are closed. The normally open contact (NO) is true (closed) when the input or output
status bit controlling the contact is 1. The normally closed contact (NC) is true (closed) when
the input or output status bit controlling the contact is 0.
Figure 6.39 Contacts symbol

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Coils
Coils represent relays that are energized when power flows to them. When a coil is energized,
it causes a corresponding output to turn on by changing the state of the status bit controlling
that output to 1. That same output status bit may be used to control normally open and
normally closed contacts elsewhere in the program.
Figure 6.40 Coil symbol
Boxes
Boxes represent various instructions or functions that are executed when power flows to the
box. Typical box functions are timers, counters, and math operations.
Figure 6.41 Box symbol
The inputs and outputs are all identified by their addresses, the notation used depending on
the PLC manufacturer. The Mitsubishi or Hitachi series of PLC precedes input elements by an
X and output elements by Y. The Siemens series of PLC precedes input elements by I and
output elements by a Q. The siemens notations will be used in the following examples.
Example: AND operation
Each rung or network on a ladder represents a logic operation. The following programming
example demonstrates an AND operation. Two contact closures and one output coil are
placed on network 1. They were assigned addresses I0.0, I0.1, and Q0.0. Note that in the
statement list a new logic operation always begins with a load instruction (LD). In this
example I0.0 (input 1) and (A in the statement list) I0.1 (input 2) must be true in order for
output Q0.0 (output 1) to be true. It can also be seen That I0.0 and I0.1 must be true for Q0.0
to be true by looking at the function block diagram representation.
Figure 6.42 AND operation

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Example: OR function
In this example an OR operation is used in network 1. It can be seen that if either input I0.2
(input 3) or (O in the statement list) input I0.3 (input 4), or both are true, then output Q0.1
(output 2) will be true.
Figure 6.43 OR operation
Testing a Program
Once a program has been written it needs to be tested and debugged. One way this can be
done is to simulate the field inputs with an input switches as shown in figure. The program is
first downloaded from the programming device to the CPU. The selector switch is placed in
the RUN position. The simulator switches are operated and the resulting indication is
observed on the output status indicator lamps.
Figure 6.44 PLC simulation

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Motor Starter Example
The following example involves a motor start and stop circuit. The line diagram illustrates
how a normally open and a normally closed pushbutton might be used in a control circuit. In
this example a motor started (M) is wired in series with a normally open momentary
pushbutton (Start), a normally closed momentary pushbutton (Stop), and the normally closed
contacts of an overload relay (OL).
Figure 6.45 Motor start/stop components
Program Instruction
A normally open Start pushbutton is wired to the first input (I0.0), a normally closed Stop
pushbutton is wired to the second input (I0.1), and normally closed overload relay contacts
(part of the motor starter) are connected to the third input (I0.2). The first input (I0.0), second
input (I0.1), and third input (I0.2) form an AND circuit and are used to control normally open
programming function contacts on Network 1. I0.1 status bit is logic 1 because the normally
closed (NC) Stop Pushbutton is closed. I0.2 status bit is logic 1 because the normally closed
(NC) overload relay (OL) contacts are closed. Output Q0.0 is also programmed on Network 1.
In addition, a normally open set of contacts associated with Q0.0 is programmed on Network
1 to form an OR circuit. A motor starter is connected to output Q0.0.
Figure 6.46 Ladder program in the CPU
Note that, momentarily depressing the Start pushbutton completes the path of current flow
and energizes the motor starter (M).This closes the associated (auxiliary contact located As
marker or memory variable in the PLC) contact Q0. When the Start button, the auxiliary
contacts Qo remains closed as the output is energized. The motor will run until the normally
closed Stop button is depressed, or the overload relay opens the OL contacts, breaking the
path of current flow to the motor starter and opening also its associated contact.

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6.6.4 Timers
Timers are devices that count increments of time. Traffic lights are one example where timers
are used. In this example timers are used to control the length of time between signal changes.
Figure 6.47 Timers application in traffic lights
Timers are represented by boxes in ladder logic. When a timer receives an enable, the timer
starts to time. The timer compares its current time with the preset time. The output of the
timer is logic 0 as long as the current time is less than the preset time. When the current time
is greater than the preset time the timer output is logic 1. There are three types of timers: On-
Delay (TON), Retentive On-Delay (TONR), and Off-Delay (TOF).
Figure 6.48 PLC timers types
On-Delay (TON)
When the On-Delay timer (TON) receives an enable (logic 1), at its input (IN), a
predetermined amount of time (preset time - PT) passes before the timer bit (T-bit) turns on.
The T-bit is a logic function internal to the timer and is not shown on the symbol. The timer
resets to the starting time when the enabling input goes to logic 0.
Example: Consider a switch is connected to input I0.3 and a light is connected to output
Q0.1 as shown in ladder program.
Figure 6.49 On-Delay timer

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In the above example, When the switch I3.0 is closed (logic 1), which is loaded into timer
T37. The timer T37 has a time base of 100 ms (.100 seconds). The preset time (PT) value has
been set to 150. This is equivalent to 15 seconds (.100 x 150). The associated contact T37 will
be closed after 15 seconds and the light will turn on. If the switch I0.3 were opened before 15
seconds had passed, then closed again, the timer would again begin timing at 0.
Retentive On-Delay (TONR)
The Retentive On-Delay timer (TONR) functions in a similar manner to the On-Delay timer
(TON). There is one difference. The Retentive On-Delay timer times as long as the enabling
input is on, but does not reset when the input goes off. The timer must be reset with a RESET
(R) instruction. The same example used with the On-Delay timer will be used with the
Retentive On-Delay timer. When the switch is closed at input I0.3, timer T5 (Retentive timer)
begins timing. If, for example, after 10 seconds input I0.3 is opened the timer stops. When
input I0.3 is closed the timer will begin timing at 10 seconds. The light will turn on 5 seconds
after input I0.3 has been closed the second time.
Off-Delay (TOF)
The Off-Delay timer is used to delay an output off for a fixed period of time after the input
turns off. When the enabling bit turns on the timer bit turns on immediately and the value is
set to 0. When the input turns off, the timer counts until the preset time has elapsed before the
timer bit turns off.
6.6.5 Counters
Counters used in PLCs serve the same function as mechanical counters. Counters compare an
accumulated value to a preset value to control circuit functions. Control applications that
commonly use counters include the following:
• Count to a preset value and cause an event to occur
• Cause an event to occur until the count reaches a preset value
A bottling machine, for example, may use a counter to count bottles into groups of six for
packaging.
Figure 6.50 Counters in packaging application
Counters are represented by boxes in ladder logic. Counters increment/decrement one count
each time the input transitions from off (logic 0) to on (logic 1). The counters are reset when a
RESET instruction is executed. There are three types of counters: up counter (CTU), down
counter (CTD), and up/down counter (CTUD) as shown in the following figure.

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Figure 6.51 Counters types
Up Counter (CTU)
The up counter counts up from a current value to a preset value (PV). Input CU is the count
input. Each time CU transitions from logic 0 to logic 1 the counter increments by a count of 1.
Input R is the reset. A preset count value is stored in PV input. If the current count is equal to
or greater than the preset value stored in PV, the output bit (Q) turns on (not shown).
Down Counter (CTD)
The down counter counts down from the preset value (PV) each time CD transitions from
logic 0 to logic 1. When the current value is equal to zero the counter output bit (Q) turns on
(not shown). The counter resets and loads the current value with the preset value (PV) when
the load input (LD) is enabled.
Up/Down Counter (CTUD)
The up/down counter counts up or down from the preset value each time either CD or CU
transitions from a logic 0 to a logic 1. When the current value is equal to the preset value, the
output QU turns on. When the current value (CV) is equal to zero, the output QD turns on.
The counter loads the current value (CV) with the preset value (PV) when the load input (LD)
is enabled. Similarly, the counter resets and loads the current value (CV) with zero when the
reset (R) is enabled. The counter stops counting when it reaches preset or zero.
Example: A counter might be used to keep track of the number of vehicles in a parking lot.
As vehicles enter the lot through an entrance gate, the counter counts up. As
vehicles exit the lot through an exit gate, the counter counts down. When the lot is
full a sign at the entrance gate turns on indicating the lot is full.
Figure 6.52 keep track of parking as counter application

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Up/down counter C48 is used in this example. A switch, connected to the entrance gate, has
been wired to input I0.0. A switch, connected to the exit gate, has been wired to input I0.1. A
reset switch, located at the collection booth, has been wired to input I0.2. The parking lot has
150 parking spaces. This value has been stored in the preset value (PV). The counter output
has been directed to output Q0.1. Output 2 is connected to a “Parking Lot Full” sign. As cars
enter the lot the entrance gate opens. Input I0.0 transitions from logic 0 to logic 1,
incrementing the count by one. As cars leave the lot the exit gate opens. Input I0.1 transitions
from a logic 0 to a logic 1, decrementing the count by 1. When the count has reached 150, the
output Q0.1 turns on. The “Parking Lot Full” sign illuminates. When a car exits,
decrementing the count to 149, the sign turns off. Note that LD is not used in this example.
Figure 6.53 Ladder logic diagram
6.6.6 Digital temperature controller using PLC
Consider a temperature control task involving a domestic central heating system as shown in
figure.
Figure 6.54 Central heating system
Motorized pump M2
Motorized pump M1
Radiators
Boiler temperature sensor
Boiler
Room
temperature
sensor
Hot water tank temperature sensor
Hot water
tank

- 172 -
The central heating boiler is to be thermostatically controlled and supply hot water to the
radiator system in the house and also to the hot water tank to provide hot water from the taps
in the house. Pump motors have to be switched on to direct hot water from the boiler to either,
or both, of the radiator and hot water systems according to whether the temperature sensors
from the room temperature and the hot water tank indicate that the radiators or tank need
heating. The entire system is to be controlled by a clock so that it only operates for certain
hours of day. The system has the following inputs and outputs assignments:
Inputs
• Clock signal to operate the system using boiler (I0.0)
• Boiler temperature sensor (I0.1)
• Room temperature room sensor (I0.2)
• Water tank temperature sensor (I0.3)
Outputs
• Boiler heating system (Q0.0)
• Pump (M1) for feeding radiators heating system (Q0.1)
• Pump (M2) for feeding the water tank (Q0.2)
The Ladder diagram for this system is given as
Figure 6.55 Central heating system (ladder diagram)
The ladder diagram consists of three networks (rungs):
Network 1: Boiler heating is working when there is a request from room or tank temperature
sensors provided that the clock signal is active and that the boiler temperature sensor indicates
that the water is not hot enough.
Network 2: Pump M1 works when there is a request from the room temperature sensor
provided that the boiler is activated and there is a hot water inside it (see the associated
contact Q0.0, it is a memory variable and not external contact).
Network 3: Pump M2 works when there is a request from the water tank temperature sensor
provided that the boiler is activated and there is a hot water inside it.
Q0.0I0.0 I0.1I0.2
I0.3
I0.2Q0.0
I0.3Q0.0
( )
( )
( )
Q0.1
Q0.2

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6.7 Basic concepts (MCQ)
Place the later of statement that best completes the sentence in space provided.
1] Digital control systems use ____________ to interface with analog measurements
A) ADC
B) DAC
C) Holding device
2] Aliasing phenomenon occurs when the sampling frequency is _______ the analog
waveform frequency
A) Equal to
B) Double
C) Greater than
3] In practice, the choice of sampling period has ____________ limits
A) Lower
B) Upper
C) Lower and upper
4] MSB in a weighted resistor R/2n
R DAC, is connected to____________
A) R
B) 2R
C) 2n
R
5] The fastest ADC is ____________circuit
A) Dual slop
B) Successive Approximation
C) Flash
6] The conversion time of a 6-bit successive approximation ADC is _____ clock periods
A) 4
B) 6
C) 8
7] The ADC that has a serial output is ____________
A) Delta Sigma
B) Tracking
C) Flash

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8] The disadvantage of a flash type ADC is the ____________
A) Conversion time
B) Comparators
C) Number of components
9] A switch or a pushbutton is a ____________ input.
A) Discrete
B) Analog
C) Digital
10] A lamp or a solenoid is an example of a ___________output.
A) Discrete
B) Analog
C) Digital
11] The ____________ makes decisions and executes control instructions based on the input
signals.
A) CPU
B) Input module
C) Power supply
12] ____________ is a PLC programming language that uses components resembling
elements used in a line diagram.
A) Ladder logic diagram
B) Statement list
C) Function block diagram
13] A ____________ consists of one or more instructions that accomplish a task.
A) Hardware
B) Function module
C) Control program
14] When talking about computer or PLC memory, 1K refers to ____________ bits, bytes, or
words.
A) 256
B) 1024
C) 2048
15] Software that is placed in hardware is called ____________ .
A) Firmware
B) Instructions
C) Words

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16] Which of the following is not required when creating or changing a PLC program?
A) PLC
B) Programming Device
C) Printer
17] One byte is made up of ____________ .
A) 2 bits
B) 8 bits
C) 16 bits
18] The binary equivalent of a decimal 5 is ____________ .
A) 11
B) 100
C) 101
19] An input that is either On or Off is a/an ____________ input.
A) analog
B) discrete
C) normally open
20] A programming language that uses symbols resembling elements used in hard-wired
control line diagrams is referred to as a ____________ .
A) ladder logic diagram
B) statement list
C) PLC scan
21] A type of memory that can be read from but not written to is ____________ .
A) RAM
B) ROM
C) Firmware
22] ____________ is used to temporarily override the input or output status in order to test
and debug the program.
A) Transmit
B) Forcing
C) PLC scan

- 176 -
6.8 Problems
1] Convert the following binary numbers into decimal and hexadecimal
1011012
0101102
1111012
2] Convert the following decimal numbers into binary and hexadecimal
2110
63010
42710
3] A 6-bit DAC has an input of 1001012 and uses a 10 volt reference. Find the output voltage
produced
4] A 4-bit DAC must have a 8 volt output when all inputs are high. Find the required
reference voltage
5] A 12 bit DAC with 5 volt reference. What output voltage results from digital inputs of
4A6H, 02BH, and D5DH?
6] An ADC that will encode pressure data is required. The input signal is 666.6 mV/psi. If a
resolution of 0.5 psi is required. Find the number of bits necessary for the DAC knowing
that the reference is 10 volts.
7] An 8-bit ADC has a 8 volt reference volt. Find the output code for inputs of 3.4 volts and
6.7 volts.
8] A digital system has ADC conversion time as 33µs, computer processing time is 450µs,
and DAC takes 3.1 µs. Compute the minimum sampling period for this system?
9] A 10 bit, ADC with reference 5 volts and a conversion time of 44µs will be used to collect
data on time constant measurement. Thus the input will be of the form
)e-4(1V(t) -t/τ
=
What is the minimum value of τ for which reliable data samples can be taken if no S/H
circuit is used?
10] Draw a block diagram for the PLC showing the main functional items.
11] In a home water reservoir system, a motorized pump is used to feed the water in the tank.
The sensor S1 is used to indicate the maximum water kevel, while the sensor S2 is used to
indicate the water minimum level. Draw the ladder diagram to control the pump operation
in automatic mode.

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12] For the PLC ladder program shown in the following figure, state what input conditions
have to be met in each case for there to be an output from Q0.0 and Q0.1.
Figure 6.56 Problem 12
13] In the following figure, a tank will be filled with two chemicals, mixed, and then
drained. When the Start Button is pressed at input I0.0, the program starts pump 1
controlled by output Q0.0. Pump 1 runs for 5 seconds, filling the tank with the first
chemical, then shuts off. The program then starts pump 2, controlled by output Q0.1.
Pump 2 runs for 3 seconds filling the tank with the second chemical. After 3 seconds,
pump 2 shuts off. The program starts the mixer motor, connected to output Q0.2 and
mixes the two chemicals for 60 seconds. The program then opens the drain valve
controlled by output Q0.3, and starts pump 3 controlled by output Q0.4. Pump 3 shuts
off after 8 seconds and the process stops. A manual Stop switch is also provided at input
I0.1. Draw the ladder logic diagram to control the above sequence.
Figure 6.57 Chemical mixer problem
Q0.0
Q0.1
I0.2
I0.1I0.0
I0.3Q0.0
( )
( )

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