The following is the verilog code for a 15 bit 2 to 1 multiplexer. W.pdf

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The following is the verilog code for a 15 bit 2 to 1 multiplexer. When the selector is 0 the output f is i0 and when the selector is 1 the output is i1. module mux2to1(i0, i1, s, f); input i0, i1, s; outputf; assignf= s ? i1 : i0; endmodule Modify this code to build a 15 bit 4 to 1 multiplexer. The multiplexer will! have the following specification: Four 15 bit data inputs, W0, W1, W2 and W3. One 25 bit selector input, S[1..0]. One 15 bit output, F. When S [1..0] = 00 the output will be W0. When S [1..0] = 01 the output will be W1. When S [1..0] = 10 the output will be W2. When S [1..0] = 11 the output will beW3. Solution module mux41(W0,W1,W2,W3,S,F); input [14:0]W0; input [14:0]W1; input [14:0]W2; input [14:0]W3; input [1:0] s; output [14:0] F; reg [14:0] F; always @(*) //It includes all Inputs. begin case (S) 2\'b00 : F = w0; 2\'b01 : F = W1; 2\'b10 : F = W2; 2\'b11 : F = W3; endcase end endmodule.

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