22cs201 COMPUTER ORGANIZATION AND ARCHITECTURE

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22CS201
Computer Organization and Architecture
Module – II
Dr.A.Kathirvel, Dean, Computing Cluster
Sri Krishna College of Technology, Coibatore

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22CS201 Computer Organization and Architecture
Module II - Parallel Processors and Memory Organization
CPU control unit design: Hardwired and micro-programmed design approaches,
Peripheral devices and their characteristics: Input-output subsystems, I/O device
interface, I/O transfers program controlled, interrupt driven and DMA, privileged
and non-privileged instructions, software interrupts and exceptions. Programs and
processes-role of interrupts in process state transitions, I/O device interfaces -
SCII, USB. Basic concepts of pipelining, throughput and speedup, pipeline
hazards.
Dr.A.Kathirvel, Professor & DEAN,
DCSE, SKCT
Kathirvel.a@skct.edu.in

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Module II
Text Books:
1. David A. Patterson and John L. Hennessy, “Computer
Organization and Design: The Hardware/Software Interface”, 6th
Edition, Morgan Kaufmann/Elsevier, 2020.
2. 2. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig
Manjikian, “Computer Organization and Embedded Systems”,
McGraw- Hill, 6th Edition 2017.
Reference Books:
1. John P. Hayes, “Computer Architecture and Organization”,
McGraw-Hill, 3rd Edition, 2017
2. William Stallings, “Computer Organization and Architecture
Designing for Performance”, 11th Edition, Pearson Education
2018.
3. Vincent P. Heuring and Harry F. Jordan, “Computer System
Design and Architecture”, 2nd Edition, Pearson Education 2004.

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Session Topic
3.1 Introduction to x86 architecture
3.2 Datapath, Instruction fetch & execute
3.3 hardwired design approaches
3.4 micro-programmed design approaches
3.5 Input-output subsystems, I/O device interface
3.6 I/O transfers–program controlled I/O
3.7 I/O transfers– interrupt driven I/O
3.8 I/O transfers– DMA
3.9 privileged and non-privileged instructions
3.10 software interrupts and exceptions
3.11 Programs and processes
3.12 role of interrupts in process state transition
3.13 I/O device interfaces
3.14 SCII.
3.15 USB.
MODULE 3 - CONTROL UNIT & I/O TRANSFER

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3.1 INTRODUCTION TO X86 ARCHITECTURE
Content
• Introduction
• Basic properties of the x86 architecture
• Data types
• Registers
• x86 instruction format
• x86 instruction set

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Introduction
• x86 is a family of instruction set architectures initially developed by Intel based
on the Intel 8086 microprocessor
• x86 is an Intel CPU architecture that originated with the 16-bit 8086 processor in
1978.
• Today, the term "x86" is used generally to refer to any 32-bit (IA-32) processor
compatible with the x86 instruction set.
• In its 40 years of existence, the x86 architecture has added many new features
while remaining almost entirely backward-compatible, which is a remarkable
achievement.
• Modern 64-bit processors are generally referred to as x86_64

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Basic properties of the x86 architecture
• The x86 architecture is a variable instruction length (typical 2 or 3 bytes, some are single-
byte, others up to 15 bytes).
• Primarily "CISC" design with emphasis on backward compatibility.
• Byte-addressing is enabled and words are stored in memory with little-endian byte order
• Native integer sizes for arithmetic and memory addresses (or offsets) is 16, 32 or 64 bits
depending on architecture generation
• Floating point (separate prior to 80486, built-in ever since) instructions and registers for
floating point operations
• Pipelining and Superscalar features (starting with Pentium) added extra decoding steps to
split most instructions into micro-operations and executed in several execution units.
• Simultaneous multithreading

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Data types
• Integer
– x86 has 8,16,32 and 64-bit integers
– char, short, int, long long int
– Implicitly signed
– explicitly unsigned to gain an extra bit …
• Float
– 32 and 64-bit floating point numbers
– float and double
• Vector data types
– 128 bit floating point and integer vectors
– 256 bit floating point vectors

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Registers
• The 8086 offered 16-bit registers
• Four general purpose 16-bit registers
– AX, BX, CX, DX
– The ISA makes it possible to refer to the low or high bits individually
• Two 16-bit index registers (array indexing):
– SI, DI
– They contain addresses and they cannot be decomposed into High and Low
1-byte registers
• Two 16-bit special registers(Pointer registers:):
– BP: Base Pointer
– SP: Stack Pointer

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• Four 16-bit segment registers:
– CS: Code Segment
– DS: Data Segment
– SS: Stack Segment
– ES: Extra Segment
• The 16-bit Instruction Pointer (IP) register:
– Points to the next instruction to execute
– Typically not used directly when writing assembly code
• The 16-bit FLAGS registers
– Information is stored in individual bits of the FLAGS register
– Whenever an instruction is executed and produces a result, it may modify
some bit(s) of the FLAGS register
– Example: Z (or ZF) denotes one bit of the FLAGS register, which is set to 1 if
the previously executed instruction produced 0, or 0 otherwise

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• Floating point registers
– Registers ST(0) – ST(7) organized as a stack
• MMX Registers (legacy)
– 64-bit shared Shared with FPU
• Larger Registers
– 64 & 32bit
– 32 bit prefixed with “e” or “E”,
– 64 bit prefixed with “r” or “R”

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Registers

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The instruction prefix
• The instruction prefix – LOCK / Repeat
– The LOCK prefix is used to ensure exclusive use of shared memory in
multiprocessor environments.
– The repeat prefixes specify repeated operation of a string,
– There are five different repeat prefixes: REP, REPE, REPZ, REPNE, and
REPNZ.
• Segment override:
– Explicitly specifies which segment register an instruction should use.
• Operand size :
– An instruction has a default operand size of 16 or 32 bits
– the operand prefix switches between 32-bit and 16-bit operands.
• Address size:
– The processor can address memory using either 16- or 32-bit addresses.
– The address size determines the displacement size in instructions and the
size of address offsets generated during effective address calculation

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• Opcode:
– The opcode field is 1, 2, or 3 bytes in length.
• Mod R/m:
– This byte, and the next, provide addressing information.
– The Mod R/m byte specifies whether an operand is in a register or in memory;
– if it is in memory, then fields within the byte specify the addressing mode to be
used.
• SIB:(Scale Index Base)
• The SIB byte consists of three fields:
– The Scale field (2 bits) specifies the scale factor for scaled indexing;
– The Index field (3 bits) specifies the index register;
– The Base field (3 bits) specifies the base register.

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• Displacement:
– When the addressing-mode specified indicates that a displacement is
used, an 8, 16, or 32 bit signed integer displacement field is added.
• Immediate:
• Provides the value of an 8,16 or 32 bit operand.

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x86 instruction set
• Integer ALU instructions
• Data manipulation instructions
• Stack instructions
• Flag Control (EFLAG) Instructions
• jump & looping Instructions
• Segment Register Instructions
• I/O Instructions
• Miscellaneous Instructions
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Integer ALU instructions
Arithmetic
instruction
logical
instruction
bitshift
arithmetic and
logical:
rotate with and
without carry:
complement of
BCD arithmetic
instructions /
others
ADD dest,src AND
dest,src
SAL dest,count RCL
dest,count
AAA
SUB dest,src OR dest,src SHL dest,count RCR
dest,count
AAD-adjust AX
after division
MUL src XOR
dest,src
SAR dest,count ROL
dest,count
AAM
DIV src NEG dest SHR dest,count ROR
dest,count
AAS
DAA- Decimal
adjust AL after
addition
DAS

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Data manipulation instructions
data transfer instructions
MOV dest,src
XCHG dest,src
MOVSX dest,src - move string
MOVZX dest,src
CMPXCHG dest,src
CWD -Convert word to doubleword
CDQ

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Data manipulation instructions
string/array instructions
MOVS dest,src
MOVSB
MOVSW
MOVSD - Move string double-word
CMPS dest,src CMPSB
CMPSW
CMPSD
SCAS string SCASB
SCASW
SCASD - Scan string data double-word
string/array instructions
LODS src
LODSB
LODSW
LODSD
STOS dest
STOSB
STOSW
STOSD
REP
REPE
REPZ
REPNE
REPNZ

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Stack instructions & Flag Control (EFLAG) Instructions
Stack instructions Flag Control (EFLAG) Instructions
PUSH src/immed STC - Modifies flags: CF
POP dest STD - Modifies flags: DF
PUSHA STI - Modifies flags: IF
PUSHAD (386+) SAHF - Modifies flags: AF CF PF SF ZF
POPA LAHF
POPAD (386+) CLC - Modifies flags: CF
POPF CLD - Modifies flags: DF
POPFD (386+) CLI - Modifies flags: IF
CLTS

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Mnemonic Meaning Condition
JA Jump if Above CF=0 and ZF=0
JAE Jump if Aboveor Equal CF=0
JB Jump if Below CF=1
JBE Jump if Belowor Equal CF=1 or ZF=1
JC Jump if Carry CF=1
JCXZ Jump if CX Zero CX=0
JE Jump if Equal ZF=1
JG Jump if Greater(signed) ZF=0 and SF=OF
JGE Jump if Greateror Equal (signed) SF=OF
JL Jump if Less (signed) SF != OF
JLE Jump if Less or Equal (signed) ZF=1 or SF != OF
JNA Jump if Not Above CF=1 or ZF=1
JNAE Jump if Not Above or Equal CF=1
JNB Jump if Not Below CF=0
JNBE Jump if Not Below or Equal CF=0 and ZF=0
JNC Jump if Not Carry CF=0
JNE Jump if Not Equal ZF=0
JNG Jump if Not Greater (signed) ZF=1 or SF != OF
JNGE Jump if Not Greater or Equal (signed) SF != OF
JNL Jump if Not Less (signed) SF=OF
JNLE Jump if Not Less or Equal (signed) ZF=0 and SF=OF
JNO Jump if Not Overflow(signed) OF=0
JNP Jump if No Parity PF=0
JNS Jump if Not Signed (signed) SF=0
JNZ Jump if Not Zero ZF=0
JO Jump if Overflow(signed) OF=1
JP Jump if Parity PF=1
JPE Jump if Parity Even PF=1
JPO Jump if Parity Odd PF=0
JS Jump if Signed (signed) SF=1
JZ Jump if Zero
conditional jump

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Unconditional jump & looping
Unconditional jump looping
JCXZ label LOOP label INT num
JECXZ label LOOPE label CALL destination
JMP target LOOPZ label RET/RETF/RETN nBytes
LEAVE LOOPNZ label
ENTER locals, level LOOPNE label

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Segment Register & I/O Instructions
Segment Register
Instructions
I/O INSTRUCTIONS Miscellaneous Instructions
LDS dest,src IN accum,port NOP
LFS dest,src OUT port,accum XLAT translation-table
XLATB
LEA dest,src INS dest,port
INSB
INSW
INSD
CPUID
LES dest,src OUTS port,src
OUTSB
OUTSW
OUTSD
LSS dest,src

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Session Topic
3.2 Data path, Instruction fetch & execute
3.3 hardwired design approaches
3.14 SCII.
3.15 USB.
MODULE 3- CONTROL UNIT & I/O TRANSFER

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1. Data Path
• Instruction processing consists of two phases &
divide the processor hardware into two
corresponding sections
– Fetch Fetch (& Decode)
– Decode
– Execute Execute (&store)
– Store
• organize the hardware into a multi-stage structure
• each stage is completed in one clock cycle.

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1. Data Path
• An instruction is fetched in step 1 by
hardware stage 1 and placed into the IR.
• It is decoded, and its source registers are
read in step 2
• Inter-stage registers hold the results produced
in one stage so that they can be used as inputs
to the next stage during the next clock cycle.
ADD R1,R2,R3
Add LOCA,R4,R5

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Stage 1:
• instruction fetch ,decoded and stored in
register file
Stage 2:
• Data read from the register file are placed in
registers RA and RB.
Stage 3:
• Register RA provides the data to input InA
of the ALU.
• Multiplexer MuxB forwards either the
contents of RB or the immediate value in
the IR to the ALU’s second input, InB.
• The result of the computation it performs is
placed in register RZ.
ADD R1,R2,R3

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Stage 4:
• Multiplexer MuxYin selects register RZ to transfer the result to RY.
Stage 5:
• The contents of RY are transferred to the register file in step 5 and loaded into the
destination register.
• The register file is common in both stages 2 and 5.
Load & Store instruction
• For Load and Store instructions, the effective address of the memory operand is
computed by the ALU in step 3 and loaded into register RZ.
• It is sent to the memory, which is stage 4.

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Load & Store instruction
• For a Load instruction, the data read from the memory are selected by
multiplexer MuxY and placed in register RY, to be transferred to the
register file in the next clock cycle.
• For a Store instruction, data are read from the register file and placed in
register RB, and transferred to RM .
• The data to be stored are moved from RB to RM in step 3, and from
there to the memory in step 4.
• No action is taken in step 5 in this case.
LOAD R1,LOCA
STORE R1,LOCA

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2.Instruction Fetch Section
• For fetching the instructions, PC gives the addresses
• For fetching the operands, register RZ gives the address .
• MuxMA selects one of these two sources to be sent to the processor-memory interface
• The instruction address generator, updates the contents of the PC after each instruction
is fetched.
• The instruction read from the memory is loaded into the IR, where it stays until its
execution is completed and the next instruction is fetched.
• The contents of the IR are examined by the control circuitry to generate the signals
needed to control all the processor’s hardware.
• They is a block labelled Immediate, to store the immediate values.
• The Immediate block generates the extended value and forwards it to MuxB in to be
used in an ALU computation.

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Instruction fetch section

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Instruction address generator
• An adder is used to increment the PC by 4 during straight-line execution.
• It is also used to compute a branch and subroutine address.
• One adder input is PC. The second input is connected to a MuxINC.
• MuxINC selects either the constant 4 or the branch offset coming from immediate
field of the IR.
• The output of the adder is routed to the PC via a MuxPC,
• Register PC-Temp is needed to hold the contents of the PC temporarily during the
process of saving the subroutine or interrupt return address.

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Instruction address generator

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3.Instruction Fetch and Execution Steps
• The process of fetching and executing instructions is explained with example
instruction and datapath.
• E.g Add R3,R4,R5

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R4 R5 R3 Add
Add R3,R4,R5

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Step 1 :
• The instruction are fetched from the memory and placed in the IR and decoded.
Step 2 :
• The source register addresses are available in fields IR31−27 and IR26−22.
• These fields are connected to the address inputs for ports A and B of the register file.
• So,R4 and R5 are read and their contents placed in registers RA and RB, at the end of
step 2.
Step 3 :
• In the next step, MuxB input 0 line is selected , thus RB send to InB of the ALU, RA
directly send to InA of ALU.
• ALU perform an addition and result is loaded into register RZ at the end of step 3.

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Step 4 :
• MuxY selects input 0 and send the contents of RZ to RY.
• Destination address field IR21−17, is connected to port C of the register file.
Step 5 :
• Issue a write command to register file & RY is written into R3.

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Example Load R5,X(R7)

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Example Load R5,X(R7)
• X is given as an immediate value in the
instruction.
• MuxB selects 1 and the immediate value
X is added with RA ( content of R7) .
• The resulting sum is the effective
address of the operand.
R7 R5 X Load

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Example Store R6,X(R8)

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Example Store R6,X(R8)
• X is given as an immediate value in the
instruction.
• MuxB selects 1 and the immediate value
X is added with RA( content of R8) .
• The resulting sum is the effective
address of the operand.
R6 R8 X Store

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Branching
• Unconditional branch

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Branching
• Conditional branch
– Branch_if_[R5]=[R6] LOOP

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Waiting for Memory
• If the instruction or data referenced in memory are found in the cache, operation
is completed in one clock cycle.
• When the requested information is not in the cache and has to be fetched from
the main memory, several clock cycles may be needed.
• In this case processor-memory interface circuit generates a signal called Memory
• Function Completed (MFC).
Memory address←[PC], Read memory, Wait for MFC,
IR←Memory data, PC←[PC] + 4

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Session Topic
3.3 Hardwired design approaches
3.14 SCII.
3.15 USB.

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• An instruction is executed in a sequence of steps, where each step requires one
clock cycle.
• To execute these steps in instruction, the processor has to generate the control
signal in proper sequence.
• Types of Control Signal Generation
– Hardwired control
– Microprogrammed control

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Hardwired control Unit
• Hardwired system can operate at high speed.
• The setting of the control signals depends on:
– Contents of the step counter
– Contents of the instruction register
– The result of a computation or a comparison operation (for branch instruction)
– External input signals, such as interrupt requests
• The instruction decoder sets INSi signal based on decoded instruction.
• During each clock cycle, one of the outputs Ti is set to 1 to indicate which of the five
steps involved executing instructions.
• Modulo-5 counter is used.

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Hardwired control Unit
Example,
• step 1 in the instruction execution process - new instruction is fetched from the
memory.
• It is identified by signal T1
• PC as the source of the memory address,
• MEM_read is activated
• The data received from the memory are loaded into the IR.
• PC is incremented by 4

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• Counter - keeps a track on the control steps.
– Each step in the control signal sequence is completed in one clock period
• Step decoder - provides a separate signal line for each step of the control
sequence
• Instruction decoder – sets separate line INSi for each machine instruction
• Encoder - generates the control signals based on its inputs
• External input – interrupts the indication
• Conditional code Flag – Considers the condition

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Control Signal generation (datapath control signal)
• Sample control signal Zin = T1 + T6 • ADD + T4 • BR + …
Control sequence for Add (R3),R1
Step Action
1. PCout , MARin , Read,Select4,Add, Zin
:
.
6. MDRout,SelectY,Add,Zin
Control sequence for unconditional branch
1. PCout , MARin , Read,Select4,Add, Zin
:
.
4. Offset –field –of-IRout, Add, Zin

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Dealing with Memory Delay
• Most of the time, the step counter is incremented at the end of every clock cycle using
Counter_enble.
• MEM_read or a MEM_write command does not end (in one cycle)until the MFC signal
is asserted.
• To extend the duration of an execution step to more than one clock cycle, we need to
disable the step counter.
• Normally the counter is incremented by enabling a control signal - Counter_enable.
• WMFC(wait for MFC), is activated during any execution of Memory R/W oprations.
• Counter_enable should be set to 1 in only when WMFC is not asserted.
Counter_enable = WMFC + MFC

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TRY YOURSELF
Generate a control signal using logic gates for the following signals
• End
• PCin
• Zout
• PCout
(use Add R1,R2 instruction and unconditional branching instruction for reference )

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Session Topic
3.4 Micro-programmed design approaches
3.14 SCII.
3.15 USB.

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• Another type of control signal generation
• Controlled signals are generated using programmes
• Slower than hardwired approach
• Control word - A word whose individual bits
represent various control signals
• Microinstructions - The individual control
words in the micro routine
• Micro routine or Micro program - A sequence of
CW s corresponding to the instruction
• Control store – Special memory used to store the
micro routines for all instructions

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The control unit can generate the
control signals by sequentially reading
the CW’s from the control store

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control word creation:
Mark 1 for each control
signal present in a step
and mark 0 for reaming
signals
Step Action
1 PCout, MARin ,Read, Select 4,Add, Zin
2 Zout,PCin,Yin ,W FMC
3 MDRout,IRin
4 R3out,MARin,Read
5 R1out, Yin,W MFC
6 MDRout,Select Y,,,Add, Z in
7 Zout,R1in ,End
Micro
instruc
tion
PC
in
PC
out
MAR
in
Re
ad
MDR
out
IR
in
Yi
n
sel
ect
Add Z
in
Z
out
R1
out
R1
in
R3
out
W M
F C
En d
1. 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2. 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0

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Control Store for ADD R1, R2
Example problem

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TRY YOURSELF
1. An IBM company decided to upgrade their processor with a microprogrammed
control unit which should capable of generating 50 control signals. They want to
activate almost 4 control signals at a time. Design a microprogrammed control
unit with a minimum number of bits required to generate a control signal.
2. Consider the following sequence of micro operation.
MBRPC, MARX,PCY. memory MBR. Identify the operation performed
by these instruction.
( Hint :Operation- instruction fetch, instruction decode, operand fetch, conditional
branch, interrupt service )

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Session Topic
3.14 SCII.
3.15 USB.

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3.5 INPUT-OUTPUT SUBSYSTEMS, I/O DEVICE INTERFACE
I/O SUBSYSTEM
• The components of a computer system communicate with each other through an
interconnection network, which consists of circuits needed to transfer information
between the processor, the memory unit, and a number of I/O devices.
• Since the I/O devices and the memory, share the same address space, this
arrangement is called memory-mapped I/O.

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I/O SUBSYSTEM
• For example, if DATAIN is the address of a register in an input device, the
instruction
– Load R2, DATAIN // DATAIN address of a register in an input device.
– reads the data from the DATAIN register and loads them into processor
register R2.
• Similarly, the instruction Store R2, DATAOUT sends the contents of register R2
to location DATAOUT, which is a register in an output device.
Load R2,LOCA
Store R2,LOCA

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I/O Device Interface
• An I/O device is connected to the interconnection network by using a circuit,
called the device interface
• The interface includes some registers that can be accessed by the processor.
– Data register : used as a buffer for data transfers,
– Status register : hold information about the current status of the device,
– Control register : store the information that controls the operational behaviour
of the device.
• These data, status, and control registers are accessed by program instructions
as if they were memory locations.
• Transfers of information are between I/O registers and the processor registers .

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• Data can be moved from input device to memory or memory to output device.
Registers & Buses used for I/O operations
• Status Register – SIN, SOUT
• Data Registers - DATAIN, DATAOUT
• Bus – Control bus, Address bus, Data bus

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Input (Keyboard) Operations
• When a key is struck on keyboard, a character code is stored in DATAIN register
• Status register SIN =1 indicates that the valid character is present in DATAIN
• Processor reads a character and clears the SIN. (SIN=0)

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1.7.2 Output ( Printer) Operations
• A status register SOUT=1 indicates it is ready to access the character.
• Processor places the character in DATAOUT register & clears the SOUT=0.

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• Data can be moved from input device to memory or memory to output device.
Registers & Buses used for I/O operations
• Status Register – SIN, SOUT
• Data Registers - DATAIN, DATAOUT
• Bus – Control bus, Address bus, Data bus

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3.6 PROGRAM CONTROLLED I/O
• There are three modes of transfer for data, commands and status as follows:
– Programmed IO
• Using program data transfer or communication takes place
– Interrupt driven IO
• Using interrupt data transfer or communication takes place
– Direct memory access
• Using Hardware data transfer or communication takes place

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Program-Controlled I/O or polling
• The programmed I/O is simple type of I/O technique for the exchanging data or
any types of communication between the processor and the external devices.
Steps
• The processor is executing a program and encounters an instruction relating to
I/O operation.
• The processor then executes that instruction by issuing a command to the
appropriate I/O module.
• The I/O module will perform the requested action (READ/WRITE) and set the
appropriate bits in the I/O status register.
• The processor will periodically check the status of the I/O module until it find that
the operation is complete.

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I/O Commands
• Control: Used to activate a peripheral and tell it
what to do. For example, a magnetic-tape unit may
be instructed to rewind or to move forward one
record.
• Test: Used to test various status conditions
associated with an I/O module and its peripherals.
The processor will want to know that the peripheral
of interest is powered on and available for use.
• Read: Causes the I/O module to obtain an item of
data from the peripheral and place it in an internal
buffer.
• Write: Causes the I/O module to take an item of data
(byte or word) from the data bus and subsequently
transmit that data item to the peripheral.

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Program-Controlled I/O
• The rate of data transfer from the keyboard to a computer is limited by the typing
speed of the user.(few character/sec)
• The rate of output transfers from the computer to the display is much higher
( several thousand characters /sec)
• But processor can execute billions of instructions per second.
• The difference in speed between the processor and I/O devices creates the need
for mechanisms to synchronize the transfer of data between them.
mechanisms to synchronize  Signalling

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Signalling protocol
• Output
– The processor sends the first character and then waits for a signal from the
display.
– After getting signal from display, It then sends the second character, and so on.
• Input
– The processor waits for a signal indicating that a key has been pressed and that
a binary code that represents the corresponding character is available in an I/O
register associated with the keyboard.
– Then the processor proceeds to read that code

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Keyboard
• KBD_DATA 8-bit register that holds the generated character.
• KIN (1)  indicate that key has been pressed
part of an eight-bit status register, KBD_STATUS.
• When the processor reads the status flag to determine its state, we say that the
processor polls the I/O device.

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Display
• DISP_DATA 8-bit register receive that receives characters from the processor.
• DOUT (1)  indicate that register is ready to receive a next character.
part of an eight-bit status register, DISP_STATUS.
• When the processor reads the status flag to determine its state, we say that the
processor polls the I/O device.

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• Assigned hexadecimal numbers 4000 and 4010 as base addresses for the
keyboard and display, respectively.
– data registers  0x4000 / 0x4010
– status registers  0x4004 / 0x4014
– control registers  0x4008 / 0x4018
• This makes all addresses word-aligned in a 32-bit word computer.

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Input process
• Key is pressed
– ASCII-encoded character is placed into the KBD_DATA register.
– Set KIN flag (KIN=1).
• Processor is executing the I/O program which continuously checks the state of
the KIN flag.
• When it detects that KIN is set to 1, it transfers the contents of KBD_DATA into a
processor register.
• KIN must be cleared to 0, which is usually done automatically by the interface
circuit.
• If a second character is entered at the keyboard, KIN is again set to 1 and the
process repeats.

12
• Input process
• RISC –style instruction
LoadByte R5, KBD_DATA

13
Output process
• When DOUT is equal to 1, the display is ready to receive a character.
• The processor monitors DOUT, and when DOUT is equal to 1,
– The processor transfers an ASCII-encoded character to DISP_DATA.
– Clears DOUT to 0.
• When the display device is ready to receive a second character, DOUT is again
set to 1.
• This can be achieved by performing the operations

14
• Output process
• RISC –style instruction
StoreByte R5, DISP_DATA

15
Advantages & Disadvantages of Programmed I/O
Advantages
• Simple to implement
• Very little hardware support
Disadvantages
• Busy waiting
• Ties up CPU for long period with no useful work

16
• RISC-Style I/O Program

17
• CISC-Style I/O Program

19
• Bus arbitration
• https://www.youtube.com/watch?v=Xi_jRzyq42g
• Gate bookview
• https://www.youtube.com/watch?v=KayPmnr-C_s
• Tutorial point view
• https://www.youtube.com/watch?v=DK4bE8OA8d8
• DMA
• https://www.youtube.com/watch?v=wi-po2SesoE

20
Session Topic
3.12 Role of interrupts in process state transition
3.14 SCII.
3.15 USB.

21
• There are three modes of transfer for data, commands and status as follows:
– Programmed IO
• Using program, data transfer or communication takes place
– Interrupt driven IO
• Using interrupt, data transfer or communication takes place
– Direct memory access
• Using Hardware, data transfer or communication takes place

22
• In program-controlled I/O, when the processor continuously monitors the status of
the device, it does not perform any useful tasks.
• An alternate approach would be for the I/O device to alert the processor when it
becomes ready.
– Do so by sending a hardware signal called an interrupt to the processor.
– At least one of the bus control lines, called an interrupt-request line is
dedicated for this purpose.
• Processor can perform other useful tasks while it is waiting for the device to be
ready.
3.7.1 Interrupts

23
3.7 INTERRUPT DRIVEN I/O
Interrupts (contd..)
Interrupt Service routine
Program 1
here
Interrupt
occurs
M
i
2
1
i 1
+
• Processor executes a routine (function) in response to an interrupt. This
routine is called Interrupt Service Routine (ISR).
• When an interrupt occurs, control must be transferred to the interrupt service
routine.

24
• If interrupt request arrives during execution of instruction i, then the processor
• first completes execution of instruction i
• The current contents of the PC( point to instruction i + 1) is stored in to the
stack.
• PC is now loaded with address of ISR, and start to execute the ISR
• At the end of the interrupt-service routine, processor reloads the PC from the
stack, causing execution to resume at instruction i+1.
Return address, or the contents of the PC are usually stored on the processor
stack.

25
• As a part of handling interrupts, the processor must inform the device that its
request has been recognized so that IO may remove its interrupt-request signal.
This is done by a special signal called interrupt – acknowledge signal.
• Saving these information(PC,PSW in stack) increases the delay between the time
an interrupt request is received and the start of execution of ISR. This delay is
called interrupt latency.
NPTEL video

26
• A single interrupt request line may be used to serve n devices.
• All devices are connected to the line via switches to ground.
• If all switches are open, the interrupt-request signals INTR1 to INTRn are inactive,
because the voltage on the interrupt – request line is Vdd. This refers to the
inactive state of the line.
3.7.2 Interrupt Hardware

27
• When a device requests an interrupt by closing its switch, the voltage on the line
drops to 0, causing the INTR received by the processor to go to 1. Since the
closing of one or more will cause the line voltage to drop to 0
• The value of INTR is the logical OR of the requests from individual devices
INTR = INTR1 + …. + INTRn
• Resistor ‘R’ is called a pullup register because it pulls the line voltage upto the
high voltage state when the switches are open.
Interrupt Hardware

28
• The arrival of an Interrupt request from an external device causes the processor
to suspend the execution of one program and start the other.
• Because interrupts can arrive at any time, they may alter the sequence of events.
Hence the processor should be provided with the facility to enable and disable
interrupts.
3.7.3 Enabling & Disabling Interrupts:

29
There are three possibilities
1. The processor hardware ignores the interrupt request line until the execution of
first instruction of ISR has been completed.
• 1st line of ISR  interrupt disable instruction
• Last line of ISR  interrupt enable instruction
2. The processor automatically disables interrupts before starting the execution
ISR. There is a bit in the processor status register (PS) called Interrupt enable (IE)
indicates whether the interrupts are enabled or not.
• IE=1  interrupt enable , IE=0  interrupt disable
• If the bit is 1 it accept the interrupts and make IE=0 to avoid further interrupts.
Enabling & Disabling Interrupts:

30
There are three possibilities
3. The processor has a special interrupt request line for which the Interrupt
handling circuit responds only to the leading edge of the signal. Such a line is called
edge triggered.
• Receive only one request
• No danger of multiple interruption
• No need to explicitly disable interrupt

31
The sequence of events involved in handling an interrupt request from a single
device is,
– The device raises an interrupt request.
– The processor interrupts the program currently being executed and saves the
contents of the PC and PS registers.
– Interrupts are disabled by clearing the IE bit in the PS to 0.
– The action requested by the interrupt is informed by the ISR.
• During which time the device is informed that its request has been recognized,
and in response, it deactivates the interrupt-request signal.
– Upon completion of the ISR, the saved contents of the PC and PS registers
are restored (enabling interrupts by setting the IE bit to 1), and execution of
the interrupted program is resumed.

32
 Multiple I/O devices may be connected to the processor.
 Some or all of these devices may be capable of generating interrupt requests.
 Additional information is needed to identify a particular device that activated the
interrupt request line.
 The status register of each device has an IRQ bit which it sets to 1 when it
requests an interrupt.
– KIRQ- interrupts request bits for the keyboard
– DIRQ- interrupt request bits for the display
3.7.4 Handling multiple devices

33
• If 2 devices have activated the line at the same time, it must be possible to break
the tie and select one of the 2 requests for service. When the ISR for the selected
device has been completed, the second request can be serviced.
 Interrupt service routine (ISR) can poll the I/O devices connected to the bus. The
first device with IRQ equal to 1 is the one that is serviced.
 Polling mechanism is easy, but time consuming to query the status bits of all the
I/O devices connected to the bus.
Handling multiple devices (contd..)

34
1.Vectored Interrupts:
• This method reduces the time involved in the polling process.
• Here, the device requesting an interrupt may identify itself directly to the processor.
• Then the processor can immediately start executing the corresponding ISR. All the
interrupt handling schemes based on this approach are called Vectored Interrupts.
• A device requesting an interrupt can identify itself if it has its own interrupt-request
signal, or if it can send a special code to the processor .
• The code supplied by the device may represent the starting address of the ISR for
that device. This address space is called Interrupt vector table.

35
D1a1, a1m1, m1ISR(D1)
D2a2, a2m2, m2ISR(D2)
.
.
.

36
2.Interrupt Nesting:
• It is necessary to accept an interrupt request from a device during the execution
of an interrupt service routine for another device.
• E.g keep track of real time clock.
• I/O devices should be organized in a priority structure. An interrupt request from a
high priority device should be accepted while the processor is servicing another
request from a lower priority device.
• A multiple level priority organization means that during execution of an ISR,
interrupt requests will be accepted from some devices but not from others,
depending upon device’s priority.
Handling multiple devices

37
• To implement this scheme, we can assign a priority level to the processor is same
as the priority of the program that is currently being executed.
• The processor accepts interrupts only from devices that have priorities higher
than its own.
• The priority of the processor is changed (raised) to that of the device either
automatically or with special instructions.
• This action disables interrupts from devices that have the same or lower level of
priority.
• However, interrupt requests from higher-priority devices will continue to be
accepted.

38
Priority arbitration
Device 1 Device 2 Device p
Processor
INTA1
I N T R 1 I N T R p
INTA p
Multiple priority scheme

39
• Each device has a separate interrupt-request and interrupt-acknowledge line.
• Each interrupt-request line is assigned a different priority level.
• Interrupt requests received over these lines are sent to a priority arbitration circuit
in the processor.
• If the interrupt request has a higher priority level than the priority of the processor,
then the request is accepted.

40
3. Simultaneous Requests
 Which interrupt request does the processor accept if it receives interrupt requests
from two or more devices simultaneously?
– Polling is simplest mechanism.
– Priority is straight forward method.
• If the I/O devices are organized in a priority structure, the processor
accepts the interrupt request from a device with higher priority.
– When vectored interrupts are used, we must ensure that only one device is
selected to send its interrupt vector code

41
Processor
Device 2
I N T R
INTA
Device n
Device 1
Polling scheme:
• If the processor uses a polling mechanism to poll the status registers of
I/O devices to determine which device is requesting an interrupt.
• In this case the priority is determined by the order in which the devices are
polled.
• The first device with status bit set to 1 is the device whose interrupt
request is accepted.
Daisy chain scheme:

42
• Devices are connected to form a daisy chain.
• Devices share common the interrupt-request line, and interrupt- acknowledge line is
connected to form a daisy chain.
• When devices raise an interrupt request, the interrupt-request line is activated.
• The processor in response, activates interrupt-acknowledge, Received by device 1,
if device 1 does not need service, it passes the signal to device 2.
• Device that is electrically closest to the processor has the highest priority.

43
4. Combination scheme:
• When I/O devices were organized into a priority structure, each device had its
own interrupt-request and interrupt - acknowledge line. ( need more wires)
• When I/O devices were organized in a daisy chain fashion, the devices shared an
interrupt-request line, and the interrupt-acknowledge propagated through the
devices.
• A combination of priority structure and daisy chain scheme can also used.

44
Device Device
circuit
Priority arbitration
Processor
Device Device
I N T R 1
I N T R p
INTA1
INTA p
• Devices are organized into groups.
• Each group is assigned a different priority level.
• All the devices within a single group share an interrupt - request line, and are
connected to form a daisy chain.

45
 Only the devices that are being used in a given program should be
allowed to generate interrupt requests.
 Idle devices must not allowed to generate interrupt request
 To control which devices are allowed to generate interrupt requests, the
interface circuit of each I/O device has an interrupt-enable bit (IE).
 The device’s interface circuit allows the device to generate an interrupt
request if IE bit is 1.
 Interrupt-enable bit (IE) in the processor status register or the priority
structure of the interrupts determines whether a given interrupt will be
accepted.
3.7.5 Controlling Device Requests :

46
Example (keyboard)
• The keyboard status register includes bits KIN and KIRQ.
• KIN is set to 1 when information placed in data register.
• The KIRQ bit is set to 1 if an interrupt request has been raised, but not
yet serviced.
• The keyboard may raise interrupt requests only when the interrupt-enable bit,
KIE, in its control register is set to 1.
• Thus, when both KIE and KIN bits are equal to 1, an interrupt request is raised
and the KIRQ bit is set to 1.

47
Example (Display)
• Bit DIE in the control register of this interface is used to enable interrupts.
• DIRQ bit in the status register of the display interface indicates whether an
interrupt request has been raised.
• we have placed KIN and KIE in bit position 1, and DOUT and DIE in position 2.

48
In summary,
• There are two independent mechanism for controlling interrupt request
• Device side
– IE bit in control register determines, whether the device is allowed to generate
interrupt request .
• Processor side
– Either IE bit in PS register or priority structures determines, whether the
interrupt request will be accepted.

49
• Four processor control registers.
1. The status register, PS, includes the interrupt-enable bit, IE, & will accept
interrupts only when this bit is set to 1.
3.7.6 Processor Control Registers

50
2. The IPS register is used to automatically save the contents of PS when an
interrupt request is received and accepted.
• At the end of the interrupt-service routine, the previous state of the processor is
automatically restored by transferring the contents of IPS into PS
3. The IENABLE register allows the processor to selectively respond to individual
I/O devices.
– When a bit is set to 1, the processor will accept interrupt requests from the
corresponding device.
4. The IPENDING register Indicates the active interrupt requests.
• This is convenient when multiple devices may raise requests at the same time.
Then, a program can decide which interrupt should be serviced first.

51
 Interrupts were caused by sending interrupt-requests by I/O devices.
 Interrupts could be used in many other situations where the execution of one
program needs to be suspended and execution of another program needs to be
started.
 In general, the term exception is used to refer to any event that causes an
interruption.
 Interrupt-requests from I/O devices is one type of an exception.
 Other types of exceptions are:
 Recovery from errors
 Debugging
 Privilege exception
Exceptions

52
1.Recovery From Errors:
 Many sources of errors in a processor. For example:
 Error in the data stored.
 Error during the execution of an instruction.
 When such errors are detected, exception processing is initiated.
 Processor takes the same steps as in the case of I/O interrupt-request.
 It suspends the execution of the current program, and starts executing an
exception-service routine.
Exceptions (contd..)

53
 Difference between handling I/O interrupt-request and handling exceptions due to
errors:
 In case of I/O interrupt-request, the processor usually completes the execution
of an instruction in progress before branching to the interrupt-service routine.
 In case of exception processing however, the execution of an instruction in
progress usually cannot be completed.

54
2.Debugging:
• Debugger uses exceptions to provide important features:
– Trace
– Breakpoints.
• Trace mode:
– Exception occurs after the execution of every instruction.
– Debugging program is used as the exception-service routine.
• Breakpoints:
– Exception occurs only at specific points selected by the user.

55
3.Privilege Exception:
• Certain instructions can be executed only when the processor is in the supervisor
mode. These are called privileged instructions.
• If an attempt is made to execute a privileged instruction in the user mode, a
privilege exception occurs.
• Privilege exception causes:
– Processor to switch to the supervisor mode,
– Execution of an appropriate exception-servicing routine.

57
Session Topic
3.12 Role of interrupts in process state transition
3.14 SCII.

58
3.8 DMA (DIRECT MEMORY ACCESS)
Direct Memory Access (DMA):
A special control unit may be provided to transfer a block of data
directly between an I/O device and the main memory, without
continuous intervention by the processor.

59
Why DMA?
• In programmed I/O and interrupt driven I/O, it is assumed that some programs
are used to transfer data between I/O device and memory
1. Several instructions are needed for each data word transfer (Load data into
processor register, then it is stored into memory.)
2. Many high speed peripheral devices have a synchronous mode of
operation.
• Not suited for transfer of large block of data at high speed.
DMA
• It is a hardware used to transfer of large block of data directly between I/O device
and memory at high speed. Without continuous CPU intervention.

60
Advantages of DMA
• No need to execute instruction to carry out the data transfer
• Maximum data transfer rate is determined by memory R/W speed or I/O data
transfer speed.
• Much faster than programmed I/O

61
Direct Memory Access
memory
Processor
System bus
Main
Keyboard
Disk/DMA
controller
Printer
DMA
controller
Disk
Disk Network
Interface

62
Direct Memory Access (contd..)
 Control unit which performs these transfers is a part of the I/O device’s
interface circuit. This control unit is called as a DMA controller.
 DMA controller performs functions that would be normally carried out by
the processor:
 For each word transferred, it provides the memory address and
generates all the control signals.
 To transfer a block of data, it increments the memory addresses and
keeps track of the number of transfers.

63
Direct Memory Access (contd..)
 DMA controller can transfer a block of data from an external device to the
memory, without any intervention from the processor.
 To initiate the DMA transfer, the processor informs the DMA controller of:
 Starting address,
 Number of words to transfer
 Direction of transfer (I/O device to the memory, or memory to the I/O device).
 On receiving this information, the DMA controller proceeds to perform the
requested operation.
 Once the DMA controller completes the DMA transfer, it informs the processor by
raising an interrupt signal.

64
DMA Registers:
• 3 type of DMA registers are
1. DMA address register holds the starting address
2. Word count register contains the number of DMA cycles (word count).
3. The third register contains the status and control flags.
• When the controller has completed transfer and ready to receive another
command, it sets the Done flag to 1.
• The R/W bit determines the direction of the transfer.
(1-Read – Mem I/O ,0-Writw)
• Bit 30 is the Interrupt Enable flag (IE) and bit 31 is IRQ bit

65
 Processor and DMA controllers have to use the bus in an interwoven fashion to
access the memory.
 DMA devices are given higher priority than the processor to access the bus.
 While a DMA transfer is taking place, the program that requested the transfer
cannot continue, and the processor can be used to execute another program.
 Data bus is now engaged with DMA controller
 Thus the OS puts the program that requested the transfer in the Blocked state
and starts the execution of another program .
 When the transfer is completed, the DMA controller informs the processor by
sending an interrupt request.
 In response, the OS puts the suspended program in the runnable state so that it
can be selected by the scheduler to continue execution

66
Steps involved
1. When CPU wants to transfer data, it initialize the DMA controller
2. When I/O device is ready for the transfer, the DMA controller sends DMA-RQ
signal to the CPU
3. CPU relinquishes control of bus and sends DMA-ACK to DMA controller.
4. DMA controller enables its bus interface, and transfers data directly to / from
memory.
5. When done, it send interrupt to CPU, and deactivates DMA-RQ signal
6. CPU again begins to use the bus to access memory.
NPTEL Video

67
Bus arbitration
• A conflict may arise if both the processor and a DMA controller try to use the bus
at the same time to access main memory.
• To resolve these conflicts, an arbitration procedure is implemented on the bus to
coordinate the activities of all devices requesting memory transfers.
• Bus arbitration
– It is the process of selecting the next device to become the bus master &
transferring the bus master ship to it.
• Bus Master
– The device that is allowed to initiate data transfers on the bus at any given
time.
• There are 2 approaches
 Centralized arbitration:
 A single bus arbiter performs the arbitration.
 Distributed arbitration:
 All devices participate in the selection of the next bus master.

68
1.Centralized Bus Arbitration
Processor
DMA
controller
1
DMA
controller
2
BG1 BG2
B R
B B S Y

69
Centralized Bus Arbitration(cont.,)
• Bus arbiter may be the processor or a separate unit connected to the bus.
• Normally, the processor is the bus master, unless it grants bus masterships to one
of the DMA controllers.
• DMA controller requests the control of the bus by asserting the Bus Request (BR)
line.
• In response, the processor activates the Bus-Grant1 (BG1) line, indicating that the
controller may use the bus when it is free.
• BG1 signal is connected to all DMA controllers in a daisy chain fashion.
• BBSY signal is 0, it indicates that the bus is busy. When BBSY becomes 1, the
DMA controller which asserted BR can acquire control of the bus.

70
Centralized arbitration (contd..)
B B S Y
BG1
BG2
Bus
master
B R
Processor DMA controller 2 Processor
T ime
DMA controller 2
asserts the BR signal.
Processor asserts
the BG1 signal
BG1 signal propagates
to DMA#2.
Processor relinquishes control
of the bus by setting BBSY to 1.
Timing Diagram

71
Centralized Bus Arbitration(cont.,)
Timing Diagram
• DMA controller 2 requests and acquires mastership and later release the bus.
• During its tenure as bus master, it may perform one/more data transfer
operations, depending on whether it is operating in the cycle stealing/block mode.
• After it releases the bus, the processor resumes bus mastership.

72
2.Distributed arbitration
 All devices waiting to use the bus participate in the selection of the next bus
master.
 Arbitration process does not depend on a central arbiter and hence distributed
arbitration has higher reliability.
 Each device is assigned a 4-bit ID number.
 All the devices are connected using 5 lines, 4 arbitration lines to transmit the ID,
and one line for the Start-Arbitration signal.
 When one or more devices request the bus, it:
 Asserts the Start-Arbitration signal.
 Places its 4-bit ID number on the arbitration lines.

73
Distributed arbitration

74
Distributed arbitration(Contd.,)
• Arbitration process:
– Each device compares the pattern that appears on the arbitration lines to its
own ID, starting with MSB.
– If it detects a difference, it transmits 0s on the arbitration lines for that and all
lower bit positions.
– The pattern that appears on the arbitration lines is the logical-OR of all the 4-
bit device IDs placed on the arbitration lines.

75
Distributed arbitration (contd..)
• Device A has the ID 5 and wants to request the bus:
- Transmits the pattern 0101 on the arbitration lines.
• Device B has the ID 6 and wants to request the bus:
- Transmits the pattern 0110 on the arbitration lines.
• Pattern that appears on the arbitration lines is the logical OR of the patterns:
- Pattern 0111 appears on the arbitration lines.

76
Distributed arbitration (contd..)
Arbitration process:
•Each device compares the pattern that appears on the arbitration lines to its own
ID, starting with MSB.
•If it detects a difference, it transmits 0s on the arbitration lines for that and all lower
bit positions.
•Device A compares its ID 5 with a pattern 0101 to pattern 0111.
•It detects a difference at bit position 1, as a result, it transmits a pattern 0100 on the
arbitration lines.
•The pattern that appears on the arbitration lines is the logical-OR of 0100 and 0110,
which is 0110.
•This pattern is the same as the device ID of B, and hence B has won the arbitration.

77
• The OR is 0111. This is compared with device A’s code from the last bit.
A OR
0 0
1 1
0 1 -not same
1 1 -same
A B OR
ARB3 0 0 0
ARB2 1 1 1
ARB1 0 1 1
ARB0 1 0 1

78
• If not same, the bit at that position and all the bits following that position are changed into
zero.
Thus,
A becomes A
0 0
1 1
0 0 changed to
1 0 zero
• This new A value is again placed on the line.
A B OR
0 0 0
1 1 1 B’s CODE
0 1 1
0 0 0
• Thus B is the winner and it is given the ownership of the bus.

79
Session Topic
3.14 SCII.
3.15 USB.

80
Types of Instructions
• Two categories: Privileged & Non-privileged
• Non-privileged instructions
– A non-privileged instruction is an instruction that any application or user can
execute.
– E.g movl, addl, call, ret
• Privileged instructions.
– A privileged instruction, is an instruction that can only be executed in kernel
mode.
– E.g insl, outb, inb, int

82
Privileged Instructions
• The Instructions that can run only in Kernel Mode are called Privileged
Instructions
characteristics
1. If any attempt is made to execute a Privileged Instruction in User Mode, then it
will not be executed and treated as an illegal instruction. The Hardware traps it to
the Operating System.
2. Before transferring the control to any User Program, it is the responsibility of the
Operating System to ensure that the Timer is set to interrupt. Thus, if the timer
interrupts then the Operating System regains the control.
Thus, any instruction which can modify the contents of the Timer is a Privileged
Instruction.

83
3. Privileged Instructions are used by the Operating System in order to achieve
correct operation.
4. Various examples of Privileged Instructions include:
– I/O instructions and Halt instructions
– Turn off all Interrupts
– Set the Timer
– Context Switching
– Clear the Memory or Remove a process from the Memory
– Modify entries in Device-status table

84
Non-Privileged Instructions
• The Instructions that can run only in User Mode are called Non-Privileged
Instructions
• Examples of Non-Privileged Instructions include:
– Reading the status of Processor
– Reading the System Time
– Generate any Trap Instruction
– Sending the final printout of Printer
• Also, it is important to note that in order to change the mode from Privileged to Non-
Privileged, we require a Non-privileged Instruction that does not generate any
interrupt.

86
3.9 PRIVILEGED AND NON-PRIVILEGED INSTRUCTIONS

87
Session Topic
3.14 SCII.
3.15 USB.

88
• Exceptions and interrupts are unexpected events which will disrupt the normal
flow of execution of instruction(that is currently executing by processor).
• An exception is an unexpected event from within the processor.
• Interrupt is an unexpected event from outside the process.

89
• Whenever an exception or interrupt occurs, the hardware starts executing the
code that performs an action in response to the exception.
• This action may involve killing a process, outputting an error message,
communicating with an external device, or horribly crashing the entire computer
system by initiating a “Blue Screen of Death” and halting the CPU.
• The instructions responsible for this action reside in the operating system kernel,
and the code that performs this action is called the interrupt handler code. Now,
We can think of handler code as an operating system subroutine.
• Then, After the handler code is executed, it may be possible to continue
execution after the instruction where the execution or interrupt occurred.

90
• Interrupt is one of the classes of Exception.
• There are 4 classes of Exception-
– interrupt,
– trap,
– fault and
– abort.
• Though, interrupt belongs to exception still there are many differences between them.
• In any computer, during its normal execution of a program, there could be events that
can cause the CPU to temporarily halt.
• Events like this are called interrupts. Interrupts can be caused by either software or
hardware faults. Hardware interrupts are called Interrupts, while software interrupts
are called Exceptions.
• Once an interrupt is raised, the control is transferred to a special sub-routine called
Interrupt Service Routine (ISR), that can handle the conditions that are raised by the
interrupt.

91
• What is Trap, Fault and Abort ?
• Trap –
It is typically a type of synchronous interrupt caused by an exceptional condition
(e.g., breakpoint, division by zero, invalid memory access).
• Fault –
Fault exception is used in a client application to catch contractually-specified
SOAP faults. By the simple exception message, you can’t identify the reason of
the exception, that’s why a Fault Exception is useful.
• Abort –
It is a type of exception occurs when an instruction fetch causes an error.

92
 Interrupts were caused by sending interrupt-requests by I/O devices.
 Interrupts could be used in many other situations where the execution of one
program needs to be suspended and execution of another program needs to be
started.
 In general, the term exception is used to refer to any event that causes an
interruption.
 Interrupt-requests from I/O devices is one type of an exception.
 Other types of exceptions are:
 Recovery from errors
 Debugging
 Privilege exception
Exceptions

93
1.Recovery From Errors:
 Many sources of errors in a processor. For example:
 Error in the data stored.
 Error during the execution of an instruction.
 When such errors are detected, exception processing is initiated.
 Processor takes the same steps as in the case of I/O interrupt-request.
 It suspends the execution of the current program, and starts executing an
exception-service routine.

94
 Difference between handling I/O interrupt-request and handling exceptions due to
errors:
 In case of I/O interrupt-request, the processor usually completes the execution
of an instruction in progress before branching to the interrupt-service routine.
 In case of exception processing however, the execution of an instruction in
progress usually cannot be completed.

95
2.Debugging:
• Debugger uses exceptions to provide important features:
– Trace
– Breakpoints.
• Trace mode:
– Exception occurs after the execution of every instruction.
• Breakpoints:
– Exception occurs only at specific points selected by the user.

96
3.Privilege Exception:
• Certain instructions can be executed only when the processor is in the supervisor
mode. These are called privileged instructions.
• If an attempt is made to execute a privileged instruction in the user mode, a
privilege exception occurs.
• Privilege exception causes:
– Processor to switch to the supervisor mode,
– Execution of an appropriate exception-servicing routine.

98
Session Topic
3.14 SCII.
3.15 USB.

99
• A program is a passive entity that has a set of codes and instructions required to
accomplish a task
• A process, on the other hand, is an active entity of a program that is started with
the execution of the program
• Thus, the process is started by the program, once it is executed
• The instructions of the program are then executed by the process

100
Program
• A program is a set of instruction codes that has been designed to complete a
certain task
• It is a passive entity stored in the secondary memory of the computer system
• A program is considered as a passive and static entity.
• A program is like a file which contains a set of instruction codes stored on a disk
in the form of an executable file
• A program contains instructions written in any programming language
• Programs have an unlimited span of time

101
Process
• A process is an instance of a program that is being currently executed
• It is a dynamic and active entity of a program
• Processes are created when the programs are executing and they reside in the
main memory
• A process exists only for a limited time, and hence gets terminated as soon as the
task completes
• A process always consists of instructions written in machine language
• A process contains temporary data, data selection, etc.

102
Program vs Process

103
Role of Interrupt in Process State Transitions
• The complete set of process states:
• Executing in user mode
• Executing in kernel mode
• Ready to run
• Sleeping in memory
• Ready to run, but in swap space (covered later)
• Sleeping in swap space
• Preempted (the process is returning from kernel to user mode, but the kernel preempts it
and does a context switch to schedule another process. Very similar to state 3)
• Newly created. Not ready run, nor sleeping. (This is the start state for all processes except
process 0)
• The process executed exit system call and is in the zombie state. The process no longer
exists, but it leaves a record containing an exit code and some timing statistics for its parent
process to collect. The zombie state is the final state of a process.

104

105
• When the parent process executes the fork system call model and it moves into a state
where it is ready to run (3 or 5) at that time the process enters the created state
• The scheduler will eventually pick the process and the process enters the 'kernel running'
state where it completes its part of the fork system call
• After the completion of the system call, it may move to the 'user running‘
• When interrupts occur (such as system call), it again moves to the state 'kernel running'
• After completing the task of the interrupt the kernel may decide to schedule another
process to execute, so the first process enters the state 'preempted‘
• The state preempted is actually same as the state ready to run in memory, but they are
denoted separately to stress that a process executing in kernel mode can be preempted
only when it is about to return to user mode
• Consequently, the kernel could swap a process from the state preempted if necessary
• Eventually, it will return to the 'user running' again

106
• When the system call is executed, it leaves the state user running and enters the state
kernel running
• If in kernel mode, the process needs to sleep for some reason (such as waiting for I/O), it
enters the state asleep in memory
• When the event on it which it has slept, happens, the interrupt handler awakens the
process, and it enters the state ready to run in memory
• Suppose the system is executing many processes that do not set at the same time into
main memory, then the swapper (process 0) swaps out a process to make space for
another process that is in the state ready to run swapped
• When forcefully takes from main memory, the process enters the state ready to run
swapped
• Finally, swapper chooses the process as most eligible to run and it re-enters the state
ready to run in memory

107
• And then when it is scheduled, it will enter the state kernel running
• When a process completes and invokes exit system call, thus entering the states kernel
running and finally, the zombie state
• Some state transitions can be managed by the users, but not all
• User can create a process
• But the user has no control over when a process transitions to sleeping in memory to
sleeping in the swap, or ready to run in memory to ready to run in the swap, etc.
• A process can make a system call to transition itself to kernel running state
• But it has no control over when it will return from kernel mode
• Finally, a process can exit whenever it wants, but that is not the only reason for exit to be
called.

108
Session Topic
3.14 SCSI
3.15 USB.

109
3.13 I/O INTERFACE CIRCUIT
Interface circuits
 An I/O interface consists of the circuitry required to connect an I/O device
to a computer bus.
 One side of the interface which connects to the computer has bus signals
for:
 Address,
 Data
 Control
 Other side of the interface which connects to the I/O device has:
 Data path and associated controls to transfer data between the
interface and the I/O device.
 This side is called as a “port”.

110
COMPUTER TO DEVICE

111
Interface circuits (contd..)
 Ports can be classified into two:
 Parallel port,
 Serial port.
• Parallel port transfers data in the form of a number of bits at a time,
normally 8 or 16 to or from the device.
• Serial port transfers and receives data one bit at a time.
• Processor communicates with the bus in the same way, whether it is
a parallel port or a serial port.
– Conversion from the parallel to serial and vice versa takes place
inside the interface circuit.

112
CLASSICAL MOTHER BOARD

113
MODERN MOTHERBOARD WITH PORTS
EMBEDDED READILY

114
1.Parallel Interface (port)
a) Keyboard Interface / input interface / Connecting a keyboard to a
processor

115
• Keyboard is connected to a processor using a parallel port.
• Processor is 32-bits and uses memory-mapped I/O and the
asynchronous bus protocol.
• On the processor side of the interface we have:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.

116
•On the keyboard side of the interface:
- Encoder circuit which generates a ASCII code for the key pressed.
- Debouncing circuit which eliminates the effect of a key bounce (a
single key stroke may appear as multiple events to a processor).
- Data lines transfer the ASCII code for the key pressed into DATAIN
register.
- Valid line changes from 0 to 1 when the key is pressed. This causes
the code to be loaded into DATAIN register and KIN to be set to 1.

117
Input Interface Circuit-circuit design for keyboard interface

118
• Two addressable locations KBD_DATA and KBD_STATUS are presents in
interface circuit.
• The keyboard status flag, KIN is presents at bit position b1 of status flag .
When the status register is read by the processor, all other bit locations appear
as containing zeros.
• Bit A2 determines which of the two registers is involved in read operation.
Hence, a multiplexer is used to select the register to be connected to the
processor bus based on address bit A2.
• A1 and A0, are not used.
• The output of the multiplexer is connected to the data lines of the bus through
a set of tri-state gates.
• The interface circuit turns the tri-state gates on only when the three signals
• Master-ready, My_address, and R/W are all equal to 1

119
• Slave-ready signal is asserted, to inform the processor that the requested
data or status information has been placed on the data lines
• KIN signal is generated using a status flag circuit.
• It is connected to line D0 of the processor bus using a three-state driver and
multiplexer.
• When the processor requests a Read operation, it places the address of the
appropriate register on the address lines of the bus.
• The address decoder examines bits A31−3, and asserts My-address, when
one of the two registers KBD_DATAor KBD_STATUS is being addressed.
• When A2 is equal to 0, Read-data is also asserted, data in KBD_DATAis
transferred to processor bus. This signal also reset the KIN flag.
• When A2 is equal to 1, Read-data is also asserted, KIN bit of
KBD_DSTATUS is transferred to D0 data line.

120
Parallel port (contd..)
b) Printer Interface / output interface / Connecting a printer to a
processor

121
• Printer is connected to a processor using a parallel port.
• Processor is 32 bits, uses memory-mapped I/O and asynchronous bus
protocol.
• On the processor side:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.

122
•On the printer side:
- Ready signal is asserts by the printer, when it is ready to accept a
character.
This causes the DOUT flag to be set to 1.
- Processor places a new character into a DISP_DATA register.
- New Data signal is asserted by the interface circuit when it places a new
character on the data lines.

123
Output Interface Circuit

124
• Data lines of the processor bus are connected to the DISP_DATA
register of the interface.
• The status flag DOUT is connected to the data line D2 using a
three-state driver.
• The three-state driver is turned on, when the control Read-status
line is 1.
• Address decoder selects the output interface using address lines
A3 through A31.
• Address line A2 determines whether the data is to be loaded into
the DISP_DATA register or status flag is to be read.
• If the Write-data line is 1, then the New-data line is set to 1.
• If the Ready line is 1, then the status flag DOUT is set to 1.

125
Serial port
• Serial port is used to connect the processor to I/O devices that
require transmission of data one bit at a time.
• Serial port communicates in a bit-serial fashion on the device side
and bit parallel fashion on the bus side.
– Transformation between the parallel and serial formats is
achieved with shift registers that have parallel access capability.

126

127
• Input shift register accepts input one bit at a time from the I/O device.
• Once all the 8 bits are received, the contents of the input shift register
are loaded in parallel into DATAIN register.
• Output data in the DATAOUT register are loaded into the output shift
register.
• Bits are shifted out of the output shift register and sent out to the I/O
device one bit at a time.
• As soon as data from the input shift reg.are loaded into DATAIN, it can
start accepting another 8 bits of data.
• Input shift register and DATAIN registers are both used at input so that
the input shift register can start receiving another set of 8 bits from the
input device after loading the contents to DATAIN, before the processor
reads the contents of DATAIN. This is called as double- buffering.

128
SATA VS PATA

129
Session Topic
3.14 SCSI
3.15 USB.

130
3.14 SCSI BUS
SCSI Bus
 The acronym SCSI stands for Small Computer System
Interface.
 It refers to a standard bus defined by the American
National Standards Institute (ANSI).
 The SCSI bus may be used to connect a variety of
devices to a computer. It is particularly well-suited for use
with disk drives.
 In the original specifications of the standard, devices such
as disks are connected to a computer via a 50-wire cable,
which can be up to 25 meters in length and can transfer
data at rates up to 5 megabytes/s.(5MBS)
50 wire cable

131
3.14 SCSI BUS
SCSI Bus
 The SCSI bus standard has undergone many revisions, and its data transfer
capability has increased very rapidly, almost doubling every two years.
 SCSI-2 and SCSI-3 have been defined, and each has several options.
 Because of various options SCSI connector may have 50, 68 or 80 pins.

132
3.14 SCSI BUS
Data Transfer
 The SCSI bus is connected to the processor bus through a SCSI controller.
 This SCSI controller uses DMA to transfer data packets from the main memory to the
device, or vice versa.
 Data and commands are transferred in the form of packets.
 To send commands or data to a device, the processor assembles the information in the
memory then instructs the SCSI controller to transfer it to the device.
 Similarly, when data are read from a device, the controller transfers the data to the
memory and then informs the processor by raising an interrupt.

133
3.14 SCSI BUS
• Communication with a disk drive differs substantially from communication
• with the main memory.
• Data are stored on a disk in blocks called sectors, where each sector may contain
several hundred bytes.
• When a data file is written on a disk, it is not always stored in contiguous sectors.
• Some sectors may already contain previously stored information; others may be
defective and must be skipped.
• Hence, a Read or Write request may result in accessing several disk sectors that
are not necessarily contiguous.
• Because of the constraints of the mechanical motion of the disk, there is a long
delay, on the order of several milliseconds, before reaching the first sector to or
from which data are to be transferred

134
3.14 SCSI BUS
scenario
 Assume that processor needs to read block of data from a disk drive and that data are
stored in disk sectors that are not contiguous.
 The processor sends a command to the SCSI controller, which causes the following
sequence of events to take place:
1. The SCSI controller contends for control of the SCSI bus.
2. When it wins the arbitration process, the SCSI controller sends a command to the
disk controller, specifying the required Read operation.
3. The disk controller cannot start to transfer data immediately. It must first move the
read head of the disk to the required sector. Hence, it sends a message to the
SCSI controller indicating that it will temporarily suspend the connection between
them. The SCSI bus is now free to be used by other devices.

135
3.14 SCSI BUS
4. The disk controller sends a command to the disk drive to move the read head to
the first sector involved in the requested Read operation. It reads the data stored
in that sector and stores them in a data buffer. When it is ready to begin
transferring data, it requests control of the bus.
5. After it wins arbitration, it re-establishes the connection with the SCSI controller,
sends the contents of the data buffer, then suspends the connection again.
6. The process is repeated to read and transfer the contents of the second disk
sector.
7. The SCSI controller transfers the requested data to the main memory and sends
an interrupt to the processor indicating that the data are now available

136
3.14 SCSI BUS
Table 4. The SCSI bus signals.
Category Name Function
Data DB(0) to
DB(7)
Data lines: Carry one b yte of information
during the information transfer phase and
iden tify device during arbitration, selection and
reselection phases
DB(P) Parit y bit for the data bus
Phase BSY Busy: Asserted when the bus is not free
SEL Selection: Asserted during selection and
reselection
Information
type
C/D Con trol/Data: Asserted during transfer of
con trol information (command, status or
message)
–
–
–
–
–
–
MSG Message: indicates that the information being
transferred is a message
–
Operation of SCSI bus from H/W point of view

137
3.14 SCSI BUS
Handshake REQ Request: Asserted by a target to request a data
transfer cycle
ACK Acknowledge: Asserted by the initiator when it
has completed a data transfer op eration
Direction of
transfer
I/O Input/Output: Asserted to indicate an input
operation (relativ e to the initiator)
Other ATN Attention: Asserted by an initiator when it
wishes to send a message to a target
RST Reset: Causes all device controls to disconnect
from the bus and assume their start-up state
–
–
–
–
–
Category Name Function
Table 4. The SCSI bus signals.(cont.)

138
3.14 SCSI BUS
Main Phases involved
 Arbitration
 A controller requests the bus by asserting BSY and by asserting it’s associated
data line
 When BSY becomes active, all controllers that are requesting bus examine
data lines
 Selection
 Controller that won arbitration selects target by asserting SEL and data line of
target. After that initiator releases BSY line.
 Target responds by asserting BSY line
 Target controller will have control on the bus from then

139
3.14 SCSI BUS
Main Phases involved
 Information Transfer
 Handshaking signals are used between initiator and target
 At the end target releases BSY line
 Reselection

140
3.14 SCSI BUS
Arbitration and selection on the SCSI bus.
• Device 6 wins arbitration and selects device 2.
Free Arbitration Selection
Targets examine ID
D B 2
D B 5
D B 6
B S Y
S E L

141
Session Topic
3.14 SCSI
3.15 USB

142
3.14 USB BUS
USB
 Universal Serial Bus (USB) is an industry standard developed through a
collaborative effort of several computer and communication companies,
including Compaq, Hewlett-Packard, Intel, Lucent, Microsoft, Nortel
Networks, and Philips.
 Speed
 Low-speed(1.5 Mb/s)
 Full-speed(12 Mb/s)
 High-speed(480 Mb/s)
 Port Limitation
 Device Characteristics
 Plug-and-play

143
3.14 USB BUS
Host computer
Root
hub
Hub
I/O
device
Hub I/O
device
I/O
device
Hub
I/O
device
I/O
device
I/O
device
Universal Serial Bus tree structure

144
3.14 USB BUS
 To accommodate a large number of devices that can be added or removed at
any time, the USB has the tree structure as shown in the figure.
 Each node of the tree has a device called a hub, which acts as an intermediate
control point between the host and the I/O devices. At the root of the tree, a root
hub connects the entire tree to the host computer. The leaves of the tree are the
I/O devices being served (for example, keyboard, Internet connection, speaker,
or digital TV)

145
3.14 USB BUS
 In normal operation, a hub copies a message that it receives from its upstream
connection to all its downstream ports. As a result, a message sent by the host
computer is broadcast to all I/O devices, but only the addressed device will
respond to that message. However, a message from an I/O device is sent only
upstream towards the root of the tree and is not seen by other devices. Hence,
the USB enables the host to communicate with the I/O devices, but it does not
enable these devices to communicate with each other.

146
3.14 USB BUS
Addressing
 When a USB is connected to a host computer, its root hub is attached to the
processor bus, where it appears as a single device. The host software
communicates with individual devices attached to the USB by sending packets
of information, which the root hub forwards to the appropriate device in the USB
tree.
 Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit
address. This address is local to the USB tree and is not related in any way to
the addresses used on the processor bus.

147
3.14 USB BUS
Addressing
 A hub may have any number of devices or other hubs connected to it, and addresses
are assigned arbitrarily. When a device is first connected to a hub, or when it is
powered on, it has the address 0. The hardware of the hub to which this device is
connected is capable of detecting that the device has been connected, and it records
this fact as part of its own status information. Periodically, the host polls each hub to
collect status information and learn about new devices that may have been added or
disconnected.
 When the host is informed that a new device has been connected, it uses a sequence
of commands to send a reset signal on the corresponding hub port, read information
from the device about its capabilities, send configuration information to the device, and
assign the device a unique USB address. Once this sequence is completed the device
begins normal operation and responds only to the new address.

148
3.14 USB BUS
USB Protocols
 All information transferred over the USB is organized in packets, where a packet consists of one or
more bytes of information. There are many types of packets that perform a variety of control functions.
 The information transferred on the USB can be divided into two broad categories: control and data.
 Control packets perform such tasks as addressing a device to initiate data transfer, acknowledging
that data have been received correctly, or indicating an error.
 Data packets carry information that is delivered to a device.
 A packet consists of one or more fields containing different kinds of information. The first field of any
packet is called the packet identifier, PID, which identifies the type of that packet.
 They are transmitted twice. The first time they are sent with their true values, and the second time with
each bit complemented
 The four PID bits identify one of 16 different packet types. Some control packets, such as ACK
(Acknowledge), consist only of the PID byte.

149
PID 0 PID 1 PID 2 PID 3 PID 0
PID 0 PID 1 PID 2 PID 3
(a) Packet identifier field
PID ADDR ENDP CRC16
8 7 4 5
Bits
(b) Token packet, IN or OUT
PID DATA CRC16
8 0 to 8192 16
Bits
(c) Data packet
USB packet format.
Control packets used for
controlling data transfer
operations are called token
packets.

150
An output transfer
ACK
Token
Data0
Token
Data1
Host Hub I/O Device
Token
Data0
ACK
ACK
Token
Data1
ACK
Time

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