TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D.

•Download as PPT, PDF•

2 likes•2,263 views

chiportal

Technology Business

2.5D/3D Chip Stacking Supply
Chain Integration
Kurt Huang, Ph.D.
Director, Corporate Marketing, UMC
ChipEx, 2013

Outline
 2.5D/3D Applications
 Ecosystem Work Flow
 Summary
P. 2

2.5D Si Interposer Stacking
 Logic/logic: FPGA, networking infrastructure
 Logic/memory: Gaming, HPC

3D Logic/Memory Stacking
- Via-Middle TSV 28nm Logic + Memory Cube
 Mobile WideIO, Computing WideIO, HMC

Never-Enough Memory Bandwidth
- Mobile AP Driving Wide IO Memory
Dimensioning use case:
 3D video streaming playback to external display via wireless
+ on-line 3D gaming local

Keeping Power Under Hood
•LPDDR3 @800Mhz
dual-channel
•LPDDR3 @800Mhz

Real Value Drives Adoption
Motivations:
 Higher BW, lower W/BW, smaller form-factor
Opportunity of return on 3D IC investment:
 Chip process node optimization
 Homogeneous partition
 Cross-node combinations
 BOM cost optimization
 Less demanding substrate/PCB,
lighter cooling assembly, ...
 Ultimately: better product, better margin
Xilinx Virtex 7
Micron HMC

Market Segment Overview
 High performance driving
2.5DIC
 Mobile AP driving 3DIC
 SoC + Mobile Memory
 Next wave:
heterogeneous 3DIC
 Logic + Memory +
Analog/RF
 Ecosystem more
complex
 Expect driving force
emerges after 3DIC
matures

Various Work Models
 Service scopes distinguished by MEOL inclusion
 Consult your foundry/OSAT
 Work flow optimization may depend on BOM cost,
stack recipe and test strategy

Foundry TSV Design Collaterals
 Consider TSV a passive device with rule decks/models
 Typical foundry engagement applies under ecosystem work flow
(UMC 2.5D Si interposer documents)

Innovations by Open Eco-System
 Wafer thinning and handling
 Thermal/stress
consideration
 Testability
 Reliability
 3D EDA tool
 Seamless business model
 Cost
 …

Evolution Of the Supply Chain
 Technology exploration
 Feasibility study
 Interface definition
 Handover criteria
 Model convergence
 Flow standarization
 Cost down
 Service differentiation
 Further innovation

UMC Ecosystem Effort
1Q1
2
2Q1
2
1Q1
3
2Q1
3

Summary
 Foundry TSV process demonstrated
 Applicable to both 2.5D/3D
 Leverage existing CMOS process technology
 Key process issues identified & conquered
 Ecosystem work flow
 Typical foundry/OSAT engagement flow applies for both
2.5D/3D, among other models
 Foundry TSV next step: ecosystem focus
 Product level reliability assessment
 3D package level reliability demonstrated for open
ecosystem model
 Potential EDA collaboration for emerging 3D tools

Thank you for your attention!
Contact: kurt_huang@umc.com

Similar to TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D.

40/28nm ESD approach On-chip ESD protection clamps for advanced 40nm and 28nm CMOS technology Despite the rising cost for IC development, EDA tools and mask sets semiconductor design companies continue to use the most advanced CMOS technology for high performance applications because benefits like lower power dissipation, increased gate density, higher speed and lower manufacturing cost per die more than compensate the higher cost. This return on investment however only pays off for ultra high volume applications. Due to the use of sensitive elements (such as ultra thin-oxide transistors, ultra-shallow junctions, narrow and thin metal layers), increased complexity through multiple voltage domains and the use of IP blocks from various vendors, a comprehensive ESD protection strategy becomes more important. This white paper presents on-chip ESD protection clamps and approaches for 40/28nm CMOS that provide competitive advantage by improved yield, reduced silicon footprint and enable advanced multimedia and wireless interfaces like HDMI, USB 3.0, SATA, WiFi, GPS and Bluetooth. The solutions are validated in tens of products running in foundry and proprietary fabrication plants.

White paper on ESD protection for 40nm/28nm

bart_keppens

JP Keynote Nikkei Embedded Processor Symposium 2002

Lee Flanagin

Genesys System - 8dec2010

Agora Group

Chrome server2 print_http_www_uni_mannheim_de_acm97_papers_soderquist_m_13736...

Léia de Sousa

This presentation demonstrates how IEC 61850 enables progressive Opex/Capex optimization through a long term asset management strategy to reduce total cost of ownership, provide evidence for regulators and assist in investment plans. By replacing manual engineering of asset performance management systems with automatic processing ensures full consistency with real assets, thus leading to better decision-making.

Asset Lifecycle Management: flexible infrastructures enabling future change

Schneider Electric

ARC White paper: Schneider Electric Introduces First ePAC, Combines PAC with...

Schneider Electric

Goal: SAFEPOWER has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement No 687902. SAFEPOWER’s goal is to enable the development of low power mixed-criticality systems through the provision of a reference architecture, platforms and tools to facilitate the development, testing, and validation of these kinds of systems according to the market needs It is expected that the SAFEPOWER reference architecture and platforms will enable the integration and partitioning of mixed-criticality applications on a single device while reducing the total power consumption by 50%, compared to the non-integrated multi-chip implementation. To address this goal, SAFEPOWER needs to address a number of technology development challenges, that will afterwards be applied to the main project outputs, namely the SAFEPOWER low power reference architecture, the platforms and tools for the development, testing, and validation of low power mixed criticality systems. PROJECT PARTNER(S):IKERLAN, S. Coop.CAF Signalling, S.L.fent Innovative Software SolutionsImperas Software Ltd.Kungliga Tekniska Högskolan (Royal Institute of Technology)SAAB ABUniversität Siegen Methods: Railway Engineering, Energy Efficiency, Multi-Core Systems, Safety-Critical Systems, Industrial Safety, Avionics, MPSOCs, NoC, Fault Tolerance, Scheduling Theory, Power Management, Dependable Systems, MIXED CRITICALITY, predictable architectures and communication, Low Power Techniques, ENERGY MINIMIZATION TECHNIQUES, Energy and Power efficiency, Low power multicore embedded systems, Fault Isolation, hypervisor Social media links: a.Twitter : https://twitter.com/SAFEPOWER_H2020 b.Linkdin : https://www.linkedin.com/groups/7045467 d. Website : http://safepower-project.eu/ d.ResearchGate : https://www.researchgate.net/project/SAFEPOWER

D1.2 analysis and selection of low power techniques, services and patterns

Babak Sorkhpour

SECURE FILE STORAGE IN THE CLOUD WITH HYBRID ENCRYPTION

IRJET Journal

Expectations for optical network from the viewpoint of system software research

Ryousei Takano

Current control systems and emulation systems (Hardware-in-the-Loop, HIL or Processor-in-the-Loop, PIL) for high-end power-electronic applications often consist of numerous components and interlinking busses: a micro controller for communication and high level control, a DSP for real-time control, an FPGA section for fast parallel actions and data acquisition, multiport RAM structures or bus systems as interconnecting structure. System-on-Chip (SoC) combines many of these functions on a single die. This gives the advantage of space reduction combined with cost reduction and very fast internal communication. Such systems become very relevant for research and also for industrial applications. The SoC used here as an example combines a Dual-Core ARM 9 hard processor system (HPS) and an FPGA, including fast interlinks between these components. SoC systems require careful software and firmware concepts to provide real-time control and emulation capability. This paper demonstrates an optimal way to use the resources of the SoC and discusses challenges caused by the internal structure of SoC. The key idea is to use asymmetric multiprocessing: One core uses a bare-metal operating system for hard real time. The other core runs a “real-time” Linux for service functions and communication. The FPGA is used for flexible process-oriented interfaces (A/D, D/A, switching signals), quasi-hard-wired protection and the precise timing of the real-time control cycle. This way of implementation is generally known and sometimes even suggested–but to the knowledge of the author’s seldomly implemented and documented in the context of demanding real-time control or emulation. The paper details the way of implementation, including process interfaces, and discusses the advantages and disadvantages of the chosen concept. Measurement results demonstrate the properties of the solution.

System on Chip Based RTC in Power Electronics

journalBEEI

Processor architecture design using 3 d integration technologies

Avinash Reddy Penugonda

Because of the increased complexity of designs in recent years, we now have multiple components on a single chip that employ independent clocks, meaning that these clocks are not synchronized. As a result, problems with Clock Domain Crossing will occur, which, if not resolved, will proliferate and destroy the entire chip. Data crossing clock domains can cause a variety of problems, including as metastability and data loss, which can lead to the device failing completely. To overcome the clock domain crossing concerns, this work presents a dual flip flop synchronizer that employs TSPC logic and is based on the SOI technology. TSPC synchronizer when implemented in SOI technology gives outstanding results. It improves the rise time by 46.15 , the fall time by 28.57 , dissipates 24.23 less power, power delay product by a huge margin of 59.20 when compared to its bulk CMOS counterpart. When implemented on a chip, it also takes up the least amount of space. All the circuits are designed in DSCH and simulated in Microwind software. Dhatrish Tewari | Mamta Khosla "A Low Power Solution to Clock Domain Crossing" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-6 | Issue-4 , June 2022, URL: https://www.ijtsrd.com/papers/ijtsrd50222.pdf Paper URL: https://www.ijtsrd.com/engineering/electronics-and-communication-engineering/50222/a-low-power-solution-to-clock-domain-crossing/dhatrish-tewari

A Low Power Solution to Clock Domain Crossing

ijtsrd

Ev24924929

IJERA Editor

The computing continuum extends the high-performance cloud data centers with energy-efficient and low-latency devices close to the data sources located at the edge of the network. However, the heterogeneity of the computing continuum raises multiple challenges related to application and data management. These include (i) how to efficiently provision compute and storage resources across multiple control domains across the computing continuum, (ii) how to decompose and schedule an application, and (iii) where to store an application source and the related data. To support these decisions, we explore in this thesis, novel approaches for (i) resource characterization and provisioning with detailed performance, mobility, and carbon footprint analysis, (ii) application and data decomposition with increased reliability, and (iii) optimization of application storage repositories. We validate our approaches based on a selection of use case applications with complementary resource requirements across the computing continuum over a real-life evaluation testbed.

Cloud, Fog, or Edge: Where and When to Compute?

Förderverein Technische Fakultät

MPEG-21-based Cross-Layer Optimization Techniques for enabling Quality of Exp...

Alpen-Adria-Universität

Enabling 3d Microelectronics Platforms Mcms

Ionela

HPPS - Final - 06/14/2007

Marco Santambrogio

Over the last decade many researchers have taken advantage of the technology boom related to the launch of the Arduino platform to make their own datalogging devices. Many of these developments ended with the first functional prototypes in which multiple electronic boards are mixed by wiring/soldering and then used in datalogging activities. In this study we present a new, simple, robust, and expandable datalogger board based on maker’s community integrations. Our datalogger board extends previous work in this area as we designed an Arduino Mega 2560 derivative integrated board that is compatible with existing developments but was also designed and implemented considering requirements such as low power consumption, expandability, and integration. Different tests were made so reliability in low temperatures and low energy needs are satisfied. Is expected that the scientific community can add this board to their tool set, as this board solves the energy problem and present an easy transition from handmade logger integrations.

CEAZA mega board: an open-source data logger for scientists

International Journal of Reconfigurable and Embedded Systems

IRJET- Reduction of Dark Silicon through Efficient Power Reduction Designing ...

IRJET Journal

imagefiltervhdl.pptx

Akbarali206563

Similar to TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D. (20)

White paper on ESD protection for 40nm/28nm

JP Keynote Nikkei Embedded Processor Symposium 2002

Genesys System - 8dec2010

Chrome server2 print_http_www_uni_mannheim_de_acm97_papers_soderquist_m_13736...

Asset Lifecycle Management: flexible infrastructures enabling future change

ARC White paper: Schneider Electric Introduces First ePAC, Combines PAC with...

D1.2 analysis and selection of low power techniques, services and patterns

SECURE FILE STORAGE IN THE CLOUD WITH HYBRID ENCRYPTION

Expectations for optical network from the viewpoint of system software research

System on Chip Based RTC in Power Electronics

Processor architecture design using 3 d integration technologies

A Low Power Solution to Clock Domain Crossing

Ev24924929

Cloud, Fog, or Edge: Where and When to Compute?

MPEG-21-based Cross-Layer Optimization Techniques for enabling Quality of Exp...

Enabling 3d Microelectronics Platforms Mcms

HPPS - Final - 06/14/2007

CEAZA mega board: an open-source data logger for scientists

IRJET- Reduction of Dark Silicon through Efficient Power Reduction Designing ...

imagefiltervhdl.pptx

Recently uploaded

Unlock the mysteries of successful Salesforce interviews in this insightful session hosted by Hugo Rosario (Salesforce Customer), a seasoned hiring manager that leads the Salesforce Department of multinational company with over 100 interviews under their belt. Step into the manager's chair and gain exclusive behind-the-scenes insights into what makes a Salesforce consultant stand out during the interview process. From deciphering the unspoken cues to mastering key strategies, we'll explore the intricacies of the interview process and provide practical tips for consultants looking to not only pass interviews but also thrive in their roles. Whether you're a seasoned professional or just starting your Salesforce journey, this session is your backstage pass to the secrets that hiring managers wish you knew.

Behind the Scenes From the Manager's Chair: Decoding the Secrets of Successfu...

CzechDreamin

Speed Wins: From Kafka to APIs in Minutes

confluent

Explore the core of Salesforce success in 'Salesforce Adoption – Metrics, Methods, and Motivation.' We will discuss essential metrics, effective methods to drive adoption, and the driving force behind user engagement and explore strategies for onboarding, training, and continuous support that empower users to navigate the platform seamlessly. By leveraging these tools, you can effectively measure adoption against your company’s goals and create an environment where users not only adopt Salesforce but actively contribute to its ongoing success.

Salesforce Adoption – Metrics, Methods, and Motivation, Antone Kom

CzechDreamin

Intrigued by why some of the world's largest companies (Netflix, Google, Cisco, Twitter, Uber etc) are using gRPC? In this demo based talk we delve into the world of gRPC in .Net, what it does and why we should use it. We compare the interface with both Rest and graphQL. We will show you how to implement grpc server-side in .net and in the web. Finally, I will show you how the tooling helps you deliver powerful interfaces and interact with them quickly and simply.

Demystifying gRPC in .Net by John Staveley

John Staveley

As an SEO expert specializing in the IPTV and VPN niches with over five years of experience, I navigate the unique challenges of these industries adeptly. My strategic approach encompasses competitive analysis, targeted keyword research, content optimization, and high-quality backlink creation. My goal is to optimize my clients' online visibility, generating targeted organic traffic and maximizing their return on investment. With a results-driven approach and a passion for innovation, I'm poised to assist my clients in thriving in an ever-evolving digital landscape. <a href="https://iptvreel.com">

THE BEST IPTV in GERMANY for 2024: IPTVreel

reely ones

PLAI - Acceleration Program for Generative A.I. Startups

Stefano

Intro in Product Management - Коротко про професію продакт менеджера

Mark Opanasiuk

This presentation dives into the practical applications of machine learning within Google's operations, providing a comprehensive overview of how to leverage AI technologies to solve real-world business challenges. Key Points Covered: - Introduction to Machine Learning at Google: Discussion on the role of ML and its evolution in enhancing Google's operational efficiency. - Experience Sharing: Insights into the team's long-term engagement with machine learning projects and the impacts on Google’s operational strategies. - Practical Applications: Real-world examples of ML applications within Google’s daily operations, providing a blueprint to adapt similar strategies. - Challenges and Solutions: Discussion on the challenges faced during the implementation of ML projects and the strategic solutions employed to overcome them. - Future of ML at Google: Insights into future trends in machine learning at Google and how they plan to continue integrating AI into their ecosystem.

Strategic AI Integration in Engineering Teams

UXDXConf

Linux Foundation Edge _ Overview of FDO Software Components _ Randy at Intel.pdf

FIDO Alliance

ASRock Industrial FDO Solutions in Action for Industrial Edge AI _ Kenny at A...

FIDO Alliance

Where to Learn More About FDO _ Richard at FIDO Alliance.pdf

FIDO Alliance

Oauth 2.0 Introduction and Flows with MuleSoft

shyamraj55

I'm excited to share my latest predictions on how AI, robotics, and other technological advancements will reshape industries in the coming years. The slides explore the exponential growth of computational power, the future of AI and robotics, and their profound impact on various sectors. Why this matters: The success of new products and investments hinges on precise timing and foresight into emerging categories. This deck equips founders, VCs, and industry leaders with insights to align future products with upcoming tech developments. These insights enhance the ability to forecast industry trends, improve market timing, and predict competitor actions. Highlights: ▪ Exponential Growth in Compute: How $1000 will soon buy the computational power of a human brain ▪ Scaling of AI Models: The journey towards beyond human-scale models and intelligent edge computing ▪ Transformative Technologies: From advanced robotics and brain interfaces to automated healthcare and beyond ▪ Future of Work: How automation will redefine jobs and economic structures by 2040 With so many predictions presented here, some will inevitably be wrong or mistimed, especially with potential external disruptions. For instance, a conflict in Taiwan could severely impact global semiconductor production, affecting compute costs and related advancements. Nonetheless, these slides are intended to guide intuition on future technological trends.

Future Visions: Predictions to Guide and Time Tech Innovation, Peter Udo Diehl

Peter Udo Diehl

This presentation focuses on the challenges and strategies of connecting problem definitions within product development. Key Points Covered: - Kayak's mission since its inception in 2004 to simplify travel by enabling easy comparisons of flights through technological solutions. - Discussion of the complexities within the travel industry, including the high expectations for personalized user experiences and the various stakeholder influences. - Emphasis on the necessity of maintaining agility and innovation within a mature company through continuous reassessment of processes. - An explanation of the importance of disciplined problem definition to prevent project failures and team inefficiencies. - Introduction of strategies for effective communication across teams to ensure alignment and comprehension at all levels of project development. - Exploration of various problem-solving methodologies, including how to handle conflicts within team settings regarding problem definitions and project directions.

Connecting the Dots in Product Design at KAYAK

UXDXConf

Syngulon’s technology expands the capacity for selection of microorganisms. The ability to select individual microbes with a behavior of interest is essential, whether for simple cloning at the bench, or for industry-scale production. Synthetic biology uses the concept of “bioengineering” to improve or modify existing genetic systems to create microbes with desired behaviors, and Syngulon uses this approach to develop its selection technologies. This selection technology is based on bacteriocins, ribosomally-produced peptides naturally made by most bacteria to kill competitive microbial species. These bacteriocins can have a limited or wide target range against other microbial species. This technology offers advantageous over antibiotic selection for several reasons: it avoids the use of antibiotics in the first place, helping to reduce the spread of antibiotic resistant microbes. The technology also increases product yield; as bacteriocins are generally smaller peptides, they do not impose a heavy metabolic burden on the producing cell. They can have a wide target specificity, helping to avoid genetic drift. Finally, our system is 100% plasmid-based (e.g. without chromosomal mutations), making it applicable for use in any E. coli strains.

Syngulon - Selection technology May 2024.pdf

Syngulon

When you think of a highly secure meeting environment, do you instantly think 'Microsoft Teams'!? Or do you think about some unknown application, troublesome UI and daunting login process...? If you think the latter - let's change that! In this session Femke will show you how using Teams Premium features can create secure, but also good looking meetings! PRETTY. Make sure your company's brand is represented before, during and after the meeting with Customization policies in place. SECURE. Lets utilize Meeting templates and Sensitivity Labels to protect your meeting and data to prevent sensitive information from being leaked. After this session, you will have a clear understanding of the capabilities of Teams Premium features and how to set up the perfect meeting that suits your organizational requirements!

ECS 2024 Teams Premium - Pretty Secure

Femke de Vroome

This talk focuses on the practical aspects of integrating various telephony systems with Salesforce, drawing on examples from implementations in the Czech scene. It aims to inform attendees about the spectrum of telephony solutions available, from small to large scale, and their compatibility with Salesforce. The presentation will highlight key considerations for selecting a telephony provider that integrates smoothly with Salesforce, including important questions to support the decision-making process. It will also discuss methods for integrating existing telephony systems with Salesforce, aimed at companies contemplating or in the process of adopting this CRM platform. The discussion is designed to provide a straightforward overview of the steps and considerations involved in telephony and Salesforce integration, with an emphasis on functionality, compatibility, and the practical experiences of Czech companies.

Integrating Telephony Systems with Salesforce: Insights and Considerations, B...

CzechDreamin

FDO for Camera, Sensor and Networking Device – Commercial Solutions from VinC...

FIDO Alliance

The Value of Certifying Products for FDO _ Paul at FIDO Alliance.pdf

FIDO Alliance

AI presentation and introduction - Retrieval Augmented Generation RAG 101

vincent683379

Recently uploaded (20)

Behind the Scenes From the Manager's Chair: Decoding the Secrets of Successfu...

Speed Wins: From Kafka to APIs in Minutes

Salesforce Adoption – Metrics, Methods, and Motivation, Antone Kom

Demystifying gRPC in .Net by John Staveley

THE BEST IPTV in GERMANY for 2024: IPTVreel

PLAI - Acceleration Program for Generative A.I. Startups

Intro in Product Management - Коротко про професію продакт менеджера

Strategic AI Integration in Engineering Teams

Linux Foundation Edge _ Overview of FDO Software Components _ Randy at Intel.pdf

ASRock Industrial FDO Solutions in Action for Industrial Edge AI _ Kenny at A...

Where to Learn More About FDO _ Richard at FIDO Alliance.pdf

Oauth 2.0 Introduction and Flows with MuleSoft

Future Visions: Predictions to Guide and Time Tech Innovation, Peter Udo Diehl

Connecting the Dots in Product Design at KAYAK

Syngulon - Selection technology May 2024.pdf

ECS 2024 Teams Premium - Pretty Secure

Integrating Telephony Systems with Salesforce: Insights and Considerations, B...

FDO for Camera, Sensor and Networking Device – Commercial Solutions from VinC...

The Value of Certifying Products for FDO _ Paul at FIDO Alliance.pdf

AI presentation and introduction - Retrieval Augmented Generation RAG 101

TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D.

1. 2.5D/3D Chip Stacking Supply Chain Integration Kurt Huang, Ph.D. Director, Corporate Marketing, UMC ChipEx, 2013

2. Outline  2.5D/3D Applications  Ecosystem Work Flow  Summary P. 2

3. 2.5D/3D Applications

4. 2.5D Si Interposer Stacking  Logic/logic: FPGA, networking infrastructure  Logic/memory: Gaming, HPC

5. 3D Logic/Memory Stacking - Via-Middle TSV 28nm Logic + Memory Cube  Mobile WideIO, Computing WideIO, HMC

6. Never-Enough Memory Bandwidth - Mobile AP Driving Wide IO Memory Dimensioning use case:  3D video streaming playback to external display via wireless + on-line 3D gaming local

7. Keeping Power Under Hood •LPDDR3 @800Mhz dual-channel •LPDDR3 @800Mhz

8. Real Value Drives Adoption Motivations:  Higher BW, lower W/BW, smaller form-factor Opportunity of return on 3D IC investment:  Chip process node optimization  Homogeneous partition  Cross-node combinations  BOM cost optimization  Less demanding substrate/PCB, lighter cooling assembly, ...  Ultimately: better product, better margin Xilinx Virtex 7 Micron HMC

9. Application Examples

10. Market Segment Overview  High performance driving 2.5DIC  Mobile AP driving 3DIC  SoC + Mobile Memory  Next wave: heterogeneous 3DIC  Logic + Memory + Analog/RF  Ecosystem more complex  Expect driving force emerges after 3DIC matures

11. Ecosystem Work Flow

12. Example 2.5D Stacking Flow

13. Various Work Models  Service scopes distinguished by MEOL inclusion  Consult your foundry/OSAT  Work flow optimization may depend on BOM cost, stack recipe and test strategy

14. Foundry TSV Design Collaterals  Consider TSV a passive device with rule decks/models  Typical foundry engagement applies under ecosystem work flow (UMC 2.5D Si interposer documents)

15. Innovations by Open Eco-System  Wafer thinning and handling  Thermal/stress consideration  Testability  Reliability  3D EDA tool  Seamless business model  Cost  …

16. Evolution Of the Supply Chain  Technology exploration  Feasibility study  Interface definition  Handover criteria  Model convergence  Flow standarization  Cost down  Service differentiation  Further innovation

17. UMC Ecosystem Effort 1Q1 2 2Q1 2 1Q1 3 2Q1 3

18. Summary

19. Summary  Foundry TSV process demonstrated  Applicable to both 2.5D/3D  Leverage existing CMOS process technology  Key process issues identified & conquered  Ecosystem work flow  Typical foundry/OSAT engagement flow applies for both 2.5D/3D, among other models  Foundry TSV next step: ecosystem focus  Product level reliability assessment  3D package level reliability demonstrated for open ecosystem model  Potential EDA collaboration for emerging 3D tools

20. BTW, Dreams Do Come True!

21. Thank you for your attention! Contact: kurt_huang@umc.com

TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D.

Recommended

Recommended

More Related Content

Similar to TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D.

Similar to TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D. (20)

More from chiportal

More from chiportal (20)

Recently uploaded

Recently uploaded (20)

TRACK A: 2.5D/3D Chip Stacking Supply Chain Integration/ Kurt Huang, Ph.D.