Chapter 4

Introduction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],§4.1 Introduction

Instruction Execution ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Multiplexers ,[object Object],[object Object]

Logic Design Basics ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],§4.2 Logic Design Conventions

Combinational Elements ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],A B Y I0 I1 Y M u x S A B Y + A B Y ALU F

Sequential Elements ,[object Object],[object Object],[object Object],D Clk Q Clk D Q

Sequential Elements ,[object Object],[object Object],[object Object],D Clk Q Write Write D Q Clk

Clocking Methodology ,[object Object],[object Object],[object Object],[object Object]

Building a Datapath ,[object Object],[object Object],[object Object],[object Object],[object Object],§4.3 Building a Datapath

Instruction Fetch 32-bit register Increment by 4 for next instruction

R-Format Instructions ,[object Object],[object Object],[object Object]

Load/Store Instructions ,[object Object],[object Object],[object Object],[object Object],[object Object]

Branch Instructions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Branch Instructions Just re-routes wires Sign-bit wire replicated

Composing the Elements ,[object Object],[object Object],[object Object],[object Object]

ALU Control ,[object Object],[object Object],[object Object],[object Object],§4.4 A Simple Implementation Scheme NOR 1100 set-on-less-than 0111 subtract 0110 add 0010 OR 0001 AND 0000 Function ALU control

ALU Control ,[object Object],[object Object],0111 set-on-less-than 101010 set-on-less-than 0001 OR 100101 OR 0000 AND 100100 AND 0110 subtract 100010 subtract 0010 add 100000 add 10 R-type 0110 subtract XXXXXX branch equal 01 beq 0010 add XXXXXX store word 00 sw 0010 add XXXXXX load word 00 lw ALU control ALU function funct Operation ALUOp opcode

The Main Control Unit ,[object Object],R-type Load/ Store Branch opcode always read read, except for load write for R-type and load sign-extend and add 0 rs rt rd shamt funct 31:26 5:0 25:21 20:16 15:11 10:6 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0

Implementing Jumps ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Jump 2 address 31:26 25:0

Performance Issues ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Pipelining Analogy ,[object Object],[object Object],§4.5 An Overview of Pipelining ,[object Object],[object Object],[object Object],[object Object]

MIPS Pipeline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Pipeline Performance ,[object Object],[object Object],[object Object],[object Object],500ps 200ps 100 ps 200ps beq 600ps 100 ps 200ps 100 ps 200ps R-format 700ps 200ps 200ps 100 ps 200ps sw 800ps 100 ps 200ps 200ps 100 ps 200ps lw Total time Register write Memory access ALU op Register read Instr fetch Instr

Pipeline Performance Single-cycle (T c = 800ps) Pipelined (T c = 200ps)

Pipeline Speedup ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Pipelining and ISA Design ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Hazards ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Structure Hazards ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Data Hazards ,[object Object],[object Object]

Forwarding (aka Bypassing) ,[object Object],[object Object],[object Object]

Load-Use Data Hazard ,[object Object],[object Object],[object Object]

Code Scheduling to Avoid Stalls ,[object Object],[object Object],lw $t1, 0($t0) lw $t2 , 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4 , 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) stall stall lw $t1, 0($t0) lw $t2 , 4($t0) lw $t4 , 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) 11 cycles 13 cycles

Control Hazards ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Stall on Branch ,[object Object]

Branch Prediction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

MIPS with Predict Not Taken Prediction correct Prediction incorrect

More-Realistic Branch Prediction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Pipeline Summary ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],The BIG Picture

MIPS Pipelined Datapath §4.6 Pipelined Datapath and Control WB MEM Right-to-left flow leads to hazards

Pipeline registers ,[object Object],[object Object]

Pipeline Operation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

WB for Load Wrong register number

Multi-Cycle Pipeline Diagram ,[object Object]

Single-Cycle Pipeline Diagram ,[object Object]

Pipelined Control (Simplified)

Pipelined Control ,[object Object],[object Object]

Data Hazards in ALU Instructions ,[object Object],[object Object],[object Object],[object Object],§4.7 Data Hazards: Forwarding vs. Stalling

Detecting the Need to Forward ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Fwd from EX/MEM pipeline reg Fwd from MEM/WB pipeline reg

Detecting the Need to Forward ,[object Object],[object Object],[object Object],[object Object]

Forwarding Conditions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Double Data Hazard ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Revised Forwarding Condition ,[object Object],[object Object],[object Object]

Load-Use Data Hazard Need to stall for one cycle

Load-Use Hazard Detection ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

How to Stall the Pipeline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Stall/Bubble in the Pipeline Stall inserted here

Stall/Bubble in the Pipeline Or, more accurately…

Datapath with Hazard Detection

Stalls and Performance ,[object Object],[object Object],[object Object],[object Object],The BIG Picture

Branch Hazards ,[object Object],§4.8 Control Hazards PC Flush these instructions (Set control values to 0)

Reducing Branch Delay ,[object Object],[object Object],[object Object],[object Object],[object Object]

Data Hazards for Branches ,[object Object],… add $4 , $5, $6 add $1 , $2, $3 beq $1 , $4 , target ,[object Object],IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB

Data Hazards for Branches ,[object Object],[object Object],beq stalled IF ID ID EX MEM WB add $4 , $5, $6 lw $1 , addr beq $1 , $4 , target IF ID EX MEM WB IF ID EX MEM WB

Data Hazards for Branches ,[object Object],[object Object],beq stalled IF ID ID ID EX MEM WB beq stalled lw $1 , addr beq $1 , $0 , target IF ID EX MEM WB

Dynamic Branch Prediction ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

1-Bit Predictor: Shortcoming ,[object Object],outer: … … inner: … … beq …, …, inner … beq …, …, outer ,[object Object],[object Object]

2-Bit Predictor ,[object Object]

Calculating the Branch Target ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Exceptions and Interrupts ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],§4.9 Exceptions

Handling Exceptions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

An Alternate Mechanism ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Handler Actions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Exceptions in a Pipeline ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Exception Properties ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Exception Example ,[object Object],[object Object],[object Object],[object Object]

Multiple Exceptions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Imprecise Exceptions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Instruction-Level Parallelism (ILP) ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],§4.10 Parallelism and Advanced Instruction Level Parallelism

Multiple Issue ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Speculation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Compiler/Hardware Speculation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Speculation and Exceptions ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Static Multiple Issue ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Scheduling Static Multiple Issue ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

MIPS with Static Dual Issue ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],n + 20 n + 16 n + 12 n + 8 n + 4 n Address WB MEM EX ID IF Load/store WB MEM EX ID IF ALU/branch WB MEM EX ID IF Load/store WB MEM EX ID IF ALU/branch WB MEM EX ID IF Load/store WB MEM EX ID IF ALU/branch Pipeline Stages Instruction type

Hazards in the Dual-Issue MIPS ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Scheduling Example ,[object Object],Loop: lw $t0 , 0($s1) # $t0=array element addu $t0 , $t0 , $s2 # add scalar in $s2 sw $t0 , 0($s1) # store result addi $s1 , $s1,–4 # decrement pointer bne $s1 , $zero, Loop # branch $s1!=0 ,[object Object],4 sw $t0 , 4($s1) bne $s1 , $zero, Loop 3 nop addu $t0 , $t0 , $s2 2 nop addi $s1 , $s1,–4 1 lw $t0 , 0($s1) nop Loop: cycle Load/store ALU/branch

Loop Unrolling ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Loop Unrolling Example ,[object Object],[object Object],3 lw $t2 , 8($s1) addu $t0 , $t0 , $s2 4 lw $t3 , 4($s1) addu $t1 , $t1 , $s2 5 sw $t0 , 16($s1) addu $t2 , $t2 , $s2 6 sw $t1 , 12($s1) addu $t3 , $t4 , $s2 8 sw $t3 , 4($s1) bne $s1 , $zero, Loop 7 sw $t2 , 8($s1) nop 2 lw $t1 , 12($s1) nop 1 lw $t0 , 0($s1) addi $s1 , $s1,–16 Loop: cycle Load/store ALU/branch

Dynamic Multiple Issue ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Dynamic Pipeline Scheduling ,[object Object],[object Object],[object Object],[object Object],[object Object]

Dynamically Scheduled CPU Results also sent to any waiting reservation stations Reorders buffer for register writes Can supply operands for issued instructions Preserves dependencies Hold pending operands

Register Renaming ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Speculation ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Why Do Dynamic Scheduling? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Does Multiple Issue Work? ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],The BIG Picture

Power Efficiency ,[object Object],[object Object],70W 8 No 1 6 1200MHz 2005 UltraSparc T1 90W 1 No 4 14 1950MHz 2003 UltraSparc III 75W 2 Yes 4 14 2930MHz 2006 Core 103W 1 Yes 3 31 3600MHz 2004 P4 Prescott 75W 1 Yes 3 22 2000MHz 2001 P4 Willamette 29W 1 Yes 3 10 200MHz 1997 Pentium Pro 10W 1 No 2 5 66MHz 1993 Pentium 5W 1 No 1 5 25MHz 1989 i486 Power Cores Out-of-order/ Speculation Issue width Pipeline Stages Clock Rate Year Microprocessor

The Opteron X4 Microarchitecture §4.11 Real Stuff: The AMD Opteron X4 (Barcelona) Pipeline 72 physical registers

The Opteron X4 Pipeline Flow ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Fallacies ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],§4.13 Fallacies and Pitfalls

Pitfalls ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Concluding Remarks ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],§4.14 Concluding Remarks

Chapter 4

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Chapter 4