This is an introduction to the Analog Device, Fully Accurate, 16 bit, UnBuffered Vout Quad SPI interface DAC: AD5066
Welcome to the training module on the AD5066. This training module introduces the AD5066 un-buffered quad SPI interface DAC.
The AD5066 quad voltage-output DAC provides 16-bit resolution with 1-LSB max differential nonlinearity (DNL). B -/ A -grades specify 1-/4-LSB max integral nonlinearity (INL). Each DAC has an individual reference input, and an unbuffered voltage output that can drive a 60-kilohm load. The low-power SPI-compatible serial interface can be clocked at up to 50 MHz. The double-buffered inputs allow all DACs to be updated simultaneously, and to be clear ed to a programmed value. Each channel can be individually powered down, resetting to zero or midscale when powered up. Operating on a single 2.7-V to 5.5-V supply, the AD5066 consumes 2.5 mA in normal mode and 0.4 µA in power-down mode. Available in a 16-lead TSSOP package, it is specified from –40°C to +125°C.
This Device sees various application areas like process control, data acquisition system, programmable voltage and current source. due to its less power consumption factor it can be used in battery operated instruments
The AD5066 is a low power, 16-bit quad-channel, unbuffered voltage output nano-DAC Reference buffers are also provided on-chip. The part uses a versatile 3-wire, low power Schmitt trigger serial interface that operates at clock rates up to 50 MHz. The AD5066 incorporates a power-on reset circuit to ensure the DAC output powers up to a known output state. The devices also have a software power-down mode that reduces the typical current consumption to typically 400 nA. it has the DAC architecture consists of two matched DAC sections.
Data is written to the AD5066 in a 32-bit word format via a 3-wire serial interface. It supports 3-wire serial interface that is compatible with SPI, QSPI, MICROWIRE, and most DSP interface standards SYNC. The write sequence begins by bringing the SYNC line low. Bringing the SYNC line low enables the DIN and SCLK input buffers. Data from the DIN line is clocked into the 32-bit shift register on the falling edge of SCLK The serial clock frequency can be as high as 50 MHz, making the AD5066 compatible with high speed DSPs. On the 32nd falling clock edge, the last data bit is clocked in, and the programmed function is executed, that is, a change in the input register contents and/or a change in the mode of operation.
The input shift register is 32 bits wide. The first four bits are don’t cares. The next four bits are the command bits, C3 to C0 followed by the 4-bit DAC address bits, A3 to A0 and finally the bit data-word. The data-word is comprised of a 16-bit input code followed by four don’t care bits These data bits are transferred to the Input register on the 32nd falling edge of SCLK. Commands can be executed on individually selected DAC channels or on all the DACs.
This page shows Interfacing the DAC to various Microcontroller / Microprocessors. The ADSP-BF53x processor family incorporates two dual-channel synchronous serial ports, SPORT1 and SPORT0, for serial and multipro-cessor communications. Using SPORT0 to connect to the AD5066. In 8051 TxD of the 80C51/80L51 drives SCLK of the AD5066, RxD drives DIN on the AD5066, and a bit-programmable pin on the port (P3.3) drives the SYNC signal. The 80C51/80L51 transmit data in 8-bit bytes only; thus, only eight falling clock edges occur in the transmit cycle.
This page gives Application information about this device in order to increase the Efficiency and to improve its performance. It is recommended to use an external voltage reference to supply the required voltage it delivers steady supply for the device. And also in certain application like process control in industrial environments it is recommended to use a galvanically isolated interface in order to avoid any hazards.
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