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Girish Deshmukh
Master Tx Mode
1. The first byte transmitted contains the slave address of the
receiving device (7 bits) and the data direction bit.
2. In this mode the data direction bit (R/W) should be 0 which means
Write.
3. The first byte transmitted contains the slave address and Write bit.
4. Data is transmitted 8 bits at a time.
5. After each byte is transmitted, an acknowledge bit is received.
6. START and STOP conditions are output to indicate the beginning
and the end of a serial transfer.
I2C Steps
1. Mode
2. Before the master transmitter mode can be entered, the I2CONSET register
must be initialized as shown in Table 133
3. I2EN must be set to 1 to enable the I2C function.
4. If the AA bit is 0, the I2C interface will not acknowledge any address when
another device is master of the bus, so it can not enter slave mode.
5. The STA, STO and SI bits must be 0.
I2C steps contd……….
1. The I2C interface will enter master transmitter mode when software
sets the STA bit
2. The I2C logic will send the START condition as soon as the bus is
free
3. After the START condition transmitted, the SI bit is SET and the
status code in the I2STAT register is 0x08
4. This status code is used to vector to a state service routine which
will load the slave address and Write bit to the I2DAT register, and
then clear the SI bit.
5. SI is cleared by writing a 1 to the SIC bit in the I2CONCLR register.
6. When the slave address and R/W bit have been transmitted and an
acknowledgment bit has been received, the SI bit is set again, and
the possible status codes now are 0x18, 0x20, or 0x38 for the master
mode
7. or 0x68, 0x78, or 0xB0 if the slave mode was enabled (by setting AA
to 1).
Master mode contd….
8. The appropriate actions to be taken for each of these
status codes are shown in Table 148 to Table 151.
Control register, I2CONSET and I2CONCLR
The I2C control register contains bits used to control the following
I2C block functions:
Start and restart of a serial transfer, termination of a serial transfer, bit
rate, address recognition and acknowledgment.
The contents of the I2C control register may be read as I2CONSET
Writing to I2CONSET will set bits in the I2C control register that
correspond to ones in the value written
Conversely, writing to I2CONCLR will clear bits in the I2C control
register that correspond to ones in the value written.
Status decoder and Status register
Status decoder and Status register
Status Codes
Status Codes
Status Codes

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Arm i2 c eeprom

  • 2. Master Tx Mode 1. The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. 2. In this mode the data direction bit (R/W) should be 0 which means Write. 3. The first byte transmitted contains the slave address and Write bit. 4. Data is transmitted 8 bits at a time. 5. After each byte is transmitted, an acknowledge bit is received. 6. START and STOP conditions are output to indicate the beginning and the end of a serial transfer.
  • 3. I2C Steps 1. Mode 2. Before the master transmitter mode can be entered, the I2CONSET register must be initialized as shown in Table 133 3. I2EN must be set to 1 to enable the I2C function. 4. If the AA bit is 0, the I2C interface will not acknowledge any address when another device is master of the bus, so it can not enter slave mode. 5. The STA, STO and SI bits must be 0.
  • 4. I2C steps contd………. 1. The I2C interface will enter master transmitter mode when software sets the STA bit 2. The I2C logic will send the START condition as soon as the bus is free 3. After the START condition transmitted, the SI bit is SET and the status code in the I2STAT register is 0x08 4. This status code is used to vector to a state service routine which will load the slave address and Write bit to the I2DAT register, and then clear the SI bit. 5. SI is cleared by writing a 1 to the SIC bit in the I2CONCLR register. 6. When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again, and the possible status codes now are 0x18, 0x20, or 0x38 for the master mode 7. or 0x68, 0x78, or 0xB0 if the slave mode was enabled (by setting AA to 1).
  • 5. Master mode contd…. 8. The appropriate actions to be taken for each of these status codes are shown in Table 148 to Table 151.
  • 6. Control register, I2CONSET and I2CONCLR The I2C control register contains bits used to control the following I2C block functions: Start and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition and acknowledgment. The contents of the I2C control register may be read as I2CONSET Writing to I2CONSET will set bits in the I2C control register that correspond to ones in the value written Conversely, writing to I2CONCLR will clear bits in the I2C control register that correspond to ones in the value written.
  • 7. Status decoder and Status register
  • 8. Status decoder and Status register