3. VLSI
VLSI is very large scale integration
technology.
It is related to the chip designing.
Chip designing is comprises of two areas:1. FRONT END
2. BACK END
VLSI uses CMOS technology
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5. Hardware Description
Languages
Basic idea is a programming language to describe
hardware
Synthesis tools allow direct implementation from HDL
code.
Combined with modern Field Programmable Gate Array
chips large complex circuits (100000s of gates) can be
implemented.
There are many HDL’s as:1. ABEL
2. AHDL
3. VHDL
4. Verilog HDL
5. System Verilog
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6. Verilog HDL
Launched
in 1984 by CADENCE.
Verilog
is Unlike VHDL is a case
sensitive language and uses
lower case.
It
is a CONCURRENT language.
COMPLEXITY
Only
of Verilog is low.
used for DIGITAL DESIGNS.
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12. Gate level modelling
The gate level structure of digital design is required.
It requires the number of gates in the design.
It also requires the way the gates are connected.
The keywords defined for gates are as:AND
XOR
OR
XNOR
NOT
BUF
NAND
BUFIF1
NOR
BUFIF0
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14. Dataflow modelling
The flow of data should be known from one point to
another.
It works on the Boolean expressions.
ASSIGN keyword is used to drive the values.
assign y=a&b;
Usually Boolean operators are used for dataflow
modelling and only the output equations are necessary
for designing.
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15. Example:Dataflow modelling
4-bit Adder with instanciation
Step 1: build a 1-bit full adder as a module
S = (a) XOR (b) XOR (Cin ) ; ( S = a^b^Cin)
Cout = (a&b) |(Cin&(a+b))
module FA_1bit (S,Cout,a,b,Cin);
begin
input a,b,Cin;
Output S, Cout;
assign Sum = a^b^Cin;
assign Carry = (a&b) | (Cin&(a^b));
Module add_1bit
endmodule
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16. 4-bit Adder
Step 2: initiate 4 instances of FA_1bit module
Cout
1-bit
Full
Adder
Cout2
1-bit
Full
Adder
S3
S2
module FA_4bits (S,Cout,A,B,Cin);
input [3:0] A, B;
input
Cin;
output [3:0]
S;
output
Cout
wire
Cout0, Cout1, Cout2
FA_1bit
FA1(S[0], Cout0,A[0],B[0],Cin);
FA_1bit
FA1(S[1], Cout1,A[1],B[1],Cout0);
FA_1bit
FA1(S[2], Cout2,A[2],B[2],Cout1);
FA_1bit
FA1(S[3], Cout,A[3],B[3],Cout2);
end
endmodule;
B0 A0
B1 A1
B2 A2
B3 A3
Cout1
1-bit
Full
Adder
S1
Cout0
1-bit
Full
Adder
Cin
S0
The inputs and the output
are 4-bits wide
we need wires to
propagate the carry from
one stage to the next
you may name the
instances with any name,
but you have to maintain
the order 16 the inputs and
of
outputs
17. Behavioral modelling
The behavior of the circuit should be known in the
terms of its inputs and outputs.
This modelling is semi-concurrent in nature.
It uses conditional statements just like in C as “if-else”
and “case” statements.
Begin….end statements are used as for sequential
execution.
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19. D Flip-Flop with Asynchronous
Reset
always@(posedge clk or negedge rst)
begin
if (!rst) a<=0;
else a<=b;
end
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20. Structural coding
It is basically not a coding style.
It
is used to connect behavioral designs
components to design more complex
circuits.
The
components of huge circuitry are
designed separately.
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21. Vending machine
It is based on FSM.
FSM is the heart of any
digital design.
According to the input
state transition occurs.
The machine has four
states like
coke,mango,orange and
lime with an initial
state.
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23. Standard Form for a
Verilog FSM
// state flip-flops
reg [2:0] state, nxt_st;
// state definitions
parameter
reset=0,S1=1,S2=2,S3=3,..
// NEXT STATE CALCULATIONS
always@(state or inputs or ...)
begin
…
next_state= ...
…
end
// REGISTER DEFINITION
always@(posedge clk)
begin
state<=next_state;
end
// OUTPUT CALCULATIONS
output= f(state, inputs)
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