8255 PPI

1. Dr. Vithalrao Vikhe Patil College of Engineering,
Ahmednagar
Department of Information Technology
Lecture on
Unit No 6
Programmable Peripheral Interface
(8255A)
Processor Architecture & Interfacing (S.E.I.T.)
Presentation By
Prof. Ms. M. S. Gunjal
Department of Information Technology

2. Learning Objectives
 List the elements of 8255A Programmable
Peripheral Interface (PPI)
 Explain its various operating modes
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3. Features of the 8255A
 The 8255A is a general purpose programmable
universal I/O interface device.
 It has been designed to interface the CPU with
its outside world such as DAC,ADC,Keyboard
etc.
 Consist of three 8-bit bidirectional I/O ports
namely Port A,Port B & Port C.
 These ports divided in two groups of 12 bits
each as Group A and Group B.
 8255 operate in 2 différent modes namely
1)Basic I/O Mode
2)BSR (bit set reset) mode
 Bit set / bit reset applicable on 8-bits ( port C)
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4. Continue….
 It is 40 pin IC.
 8 pins of 8255 used to connect 8 bit
bidirectional CPU data bus.
 Ports are used to connect peripheral devices.
 It has Read/Write control logic.
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5. Architecture of 8255A
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6. 8255A Block Functions
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 Data Bus Buffers
It is used to interface the internal 8-bit bus of
the 8255A to the system data bus.
 Read/Write Control Logic
The 8 bit data bus buffer is controlled by the
read/write control logic. The RD/WR control
logic manages all of the internal and external
transfer of both data and control words.
CS# A1 A0 Selection
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 CONTROL
REGISTE
R

7.  Ports :
There are four ports which can be configured
as either input or output. Port A is an
indivisible 8-bit port. Port B is an indivisible
8-bit port. Port C (upper) is an indivisible 4-
bit port. Port C (lower) is an indivisible 4-bit
port.
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8. April 23, 2020 8
• Group Control Logic
– The group control logic block comprises
registers that can be programmed by the
processor and combinational circuitry whose
configuration is a function of the controlling
registers. The combinational circuitry controls the
modes in which the ports operate.
– The group control logic is split into two similar
sub systems- group A control which configures
Port A and the upper 4-bits of Port C. group B
control which configures Port B and the lower 4-
bits of Port C.
8255A Block Functions

9. Mode Word Definition for the 8255A
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10. Examples of 8255A Initialization
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11. Modes in 8255A
 There are two different modes of 8255. These
modes are:
1) Bit Set Reset (BSR) Mode
2) Input / Output Modes
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12. Bit Set Reset (BSR) Mode
 Mode is used to set or reset the bits of the Port-
C only. For BSR mode always D7 will be 0. The
control register is looking like this:
 The (D3, D2, D1) will be 000 to 111. In this
mode it affects only one bit of Port C at a time.
When user set the bit, it remains set until user
unset it. The user needs to load the bit pattern
in control register to change the bit.
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13. Input Output Modes
 Mode is selected when the D7 bit of the control
register is 1.
 This mode has also three different modes.
These modes are Mode 0 and Mode 1 and Mode
2.
 The control register is looking like below in this
mode:
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14. Input Output Modes
D7 1 for IO mode and 0 for BSR mode
D6,
D 5
These are used to set port A mode. for 00, it is m0
mode, for 01, it is m2 mode and 10 or 11, it is m2
mode.
D4
1 when port A is taking input, 0 when port A is
sending output.
D3
1 when higher nibble of port C is taking input, and
0 when higher nibble is sending output.
D2
It tells the mode of Port B. For 0, it is m0 mode,
and for 1, it is m1 mode.
D1
1 when port B is taking input, 0 when port B is
sending output.
D0
1 when lower nibble of port C is taking input, and 0
when lower nibble is sending output.
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15. Mode 0 – Simple / Basic IO Mode
 In this mode all of the ports A, B and C can be
used as input or output mode. The outputs are
latched, but inputs are not latched. This mode
has interrupt handling capability.
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16. Mode 1 – Handshake Mode
 Handshake I/O mode or strobbed I/O mode. In
this mode either port A or port B can work as
simple input port or simple output port, and
port C bits are used for handshake signals
before actual data transmission. It has interrupt
handling capacity and input and output are
latched.
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17. Continue…
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Example: A CPU wants to transfer data to a
printer. In this case since speed of
processor is very fast as compared to
relatively slow printer, so before actual data
transfer it will send handshake signals to
the printer for synchronization of the speed
of the CPU and the peripherals.

18. Handshake Bits
 In order to use port A or port B for handshake input or
output operation, we initialize that port in mode 1. Some
of the pins of port C function as handshake lines.
 For port B in this mode, PC0, PC1 and PC2 pins
function as handshake lines.
 If port A is initialized as mode 1 input port, then, PC3,
PC4 and PC5 function as handshake signals. Pins PC6
and PC7 are available for use as input/output lines.
The mode 1 which supports handshaking has
following features:
 Two ports i.e. port A and B can be used as 8-bit I/O
ports.
 Each port uses three lines of port c as handshake
signal and remaining two signals can be used as I/O
ports.
 Interrupt logic is supported.
 Input and Output data are latched.
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19. Input Handshaking signals
 IBF (Input Buffer Full) - It is an output indicating that
the input latch contains information.
 STB (Strobed Input) - The strobe input loads data
into the port latch, which holds the information until it
is input to the microprocessor via the IN instruction.
 INTR (Interrupt request) - It is an output that
requests an interrupt. The INTR pin becomes logic 1
when the STB input returns to a logic 1, and is
cleared when the data is input from the port by the
microprocessor.
 INTE (Interrupt enable) - It is neither an input nor an
output; it is an internal bit programmed via the port
PC4 (port A) or PC2 (port B) bit position.
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20. Output Handshaking signals
 OBF (Output Buffer Full) - It is an output that
goes low whenever data are output(OUT) to the
port A or port B latch. This signal is set to logic 1
whenever the ACK pulse returns from the
external device.
 ACK (Acknowledge)-It causes the OBF pin to
return to a logic 1 level. The ACK signal is a
response from an external device, indicating that
it has received the data from the 82C55A port.
 INTR (Interrupt request) - It is a signal that
often interrupts the microprocessor when the
external device receives the data via the signal,
this pin is qualified by the internal INTE(interrupt
enable) bit.
 INTE (Interrupt enable) - It is neither an input
nor an output; it is an internal bit programmed
to enable or disable the INTR pin. The INTE A bit
is programmed using the PC6 bit and INTE B is
programmed using the PC2 bit.
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21. Mode 2 – Bidirectional I/O
 In this mode only Port A can work, and port B
can either be in mode 0 or mode 1, and the
port C are used for handshaking. In this mode
the inputs and outputs are latched.
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22. Thank You !!!
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