Amvdd Data Converter Fundamentals

Unit I Data Converter Fundamentals Analog and Mixed Mode VLSI Design 06EC63 Session: Jan – June 2010

Terminology ,[object Object],[object Object],[object Object]

Introduction ,[object Object],[object Object],[object Object],[object Object]

Introduction cont'd ,[object Object],[object Object]

Analog-to-digital converter ,[object Object],[object Object]

Analog-to-digital converters Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis proportionality V max = 7.5V 0V 1111 1110 0000 0010 0100 0110 1000 1010 1100 0001 0011 0101 0111 1001 1011 1101 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V 6.0V 6.5V 7.0V analog to digital 4 3 2 1 t1 t2 t3 t4 0100 0110 0110 0101 time analog input (V) Digital output digital to analog 4 3 2 1 0100 1000 0110 0101 t1 t2 t3 t4 time analog output (V) Digital input

Example: ,[object Object],[object Object],[object Object],[object Object],[object Object]

Note: ,[object Object],[object Object],[object Object],[object Object],Example contd…

Example contd… ,[object Object],[object Object],[object Object]

How many samples should one take in order to accurately represent the analog signal? ,[object Object],[object Object],[object Object]

Nyquist Criteria ,[object Object],[object Object],[object Object],[object Object]

How much resolution should we use to represent the analog signal accurately? ,[object Object],[object Object],[object Object],[object Object],[object Object]

Note: ,[object Object],[object Object],[object Object]

Sample and Hold Characteristics ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Track and Hold Circuit ,[object Object],[object Object],[object Object]

Major Errors associated with S/H Circuit ,[object Object],[object Object],[object Object]

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Major Errors associated with S/H Circuit: Sampling Mode

[object Object],[object Object],[object Object],[object Object],Major Errors associated with S/H Circuit: Hold Mode

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Major Errors associated with S/H Circuit: Hold Mode

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Major Errors associated with S/H Circuit: Hold Mode Aperture Error / Aperture jitter / Aperture Uncertainty

Ex.1) A periodic sinusoidal signal has maximum amplitude of 2V & frequency of 100KHz. If the aperture uncertainty is equal to 0.5ns, find the max. sampling error. ,[object Object],[object Object],[object Object],[object Object]

Ex.2) A S/H ckt. is supposed to have a max. sampling error of 1mV, with the aperture jitter of 1ns. If the freq. of the signal is 50KHz, find its max. possible amplitude. ,[object Object],[object Object],[object Object],[object Object]

Resolution ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],DAC Specifications contd.

[object Object],[object Object],[object Object],Resolution DAC Specifications contd.

DAC Specifications ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

Ex.3) If a 3 bit DAC is considered with V ref = 5V, and if the input word is 110, then V out is ,[object Object],[object Object],[object Object],[object Object],[object Object]

Note ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],DAC Specifications contd.

[object Object],[object Object],[object Object],DAC Specifications contd.

[object Object],[object Object],[object Object],[object Object],DAC Specifications contd.

[object Object],[object Object],[object Object],[object Object],[object Object],DAC Specifications contd.

DIFFERENTIAL NONLINEARITY ERROR (DNL) DAC Specifications contd.

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],DIFFERENTIAL NONLINEARITY ERROR (DNL) DAC Specifications contd.

[object Object],[object Object],INTEGRAL NONLINEARITY ERROR (INL) DAC Specifications contd.

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],INTEGRAL NONLINEARITY ERROR (INL) DAC Specifications contd.

INTEGRAL NONLINEARITY ERROR (INL) DAC Specifications contd.

Q. Determine the maximum DNL (in LSBs) for a 3-bit DAC, which has the following characteristics. Does the DAC have 3-bit accuracy? If not, what is the resolution of the DAC having this characteristic?

Q. Repeat the above problem for calculating the INL (in LSB’s). ,[object Object],[object Object],[object Object],[object Object],[object Object]

Q. A DAC has a reference voltage of 1,000V, and its maximum INL measures 2.5mV. What is the maximum resolution of the converter assuming that all the other characteristics of the converter are ideal? ,[object Object],[object Object],[object Object],Answer will be N= 18 as when we substitute 17 in INL(max) it is greater than 2.5mV

ADC Specifications ,[object Object],[object Object],[object Object],[object Object]

Quantization Error Q E ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],ADC Specifications

Quantization Error Q E reduced by 50% ADC Specifications

[object Object],[object Object],[object Object],[object Object],[object Object],Quantization Error Q E reduced by 50% ADC Specifications

[object Object],[object Object],DNL ADC Specifications

[object Object],ADC Specifications

IMP points derived ,[object Object],[object Object],[object Object],ADC Specifications

Missing codes ,[object Object],[object Object],[object Object],[object Object],ADC Specifications

INL ,[object Object],[object Object],ADC Specifications

Determine the INL for the ADC whose. V REF = 5V & with the following analog inputs: 0.3125V,0.9375V, 1.875V,2.1875V, 2.8125V, 3.125V, 4.0625V, 5.0V. Determine its INL also. Draw the quantization error, Q, in units of LSBs. ADC Specifications

Problem contd.. ADC Specifications

OFFSET ERROR & GAIN ERROR ADC Specifications

Aliasing ADC Specifications ,[object Object],[object Object],[object Object]

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],Aliasing ADC Specifications

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SIGNAL TO NOISE RATIO ADC Specifications

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],SIGNAL TO NOISE RATIO contd… ADC Specifications

[object Object],[object Object],[object Object],[object Object],ADC Specifications

[object Object],[object Object],[object Object],[object Object],APERTURE ERROR ADC Specifications

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],ADC Specifications

[object Object],[object Object],[object Object],[object Object],[object Object],MIXED SIGNAL LAYOUT ISSUES

[object Object],[object Object],[object Object],[object Object],[object Object],MIXED SIGNAL LAYOUT ISSUES Integrated IC at NASA

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],MIXED SIGNAL LAYOUT ISSUES

MIXED SIGNAL LAYOUT ISSUES ,[object Object],[object Object],[object Object],[object Object]

MIXED SIGNAL LAYOUT ISSUES FLOORPLANNING ,[object Object],[object Object],[object Object],[object Object],[object Object],[object Object]

MIXED SIGNAL LAYOUT ISSUES POWER SUPPLY & GROUNDING Danger: Injecting noise from digital system to the sensitive analog circuitry through the power supply & ground connections. How power supply & ground are supplied to both? R i1 & R i2 = small & non-negligible resistance of the interconnect to the pad. L s1 & L s2 = inductance of bonding wire which connects the pads to the pin on the lead frame. Voltage Spike : 1) Digital circuitry has high transient currents due to switching, small amount of resistance associated with interconnect can result in significant spikes. Low level analog signals sensitive to such interference, thus contaminating analog system. 2)Inductance of the bonding wire. Voltage across the inductor α change in current through it. Voltage spikes equating to hundreds of multi volts can result.

MIXED SIGNAL LAYOUT ISSUES POWER SUPPLY & GROUNDING

[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],[object Object],MIXED SIGNAL LAYOUT ISSUES POWER SUPPLY & GROUNDING

MIXED SIGNAL LAYOUT ISSUES FULLY DIFFERENTIAL DESIGN ,[object Object],[object Object],[object Object]

MIXED SIGNAL LAYOUT ISSUES GUARDED RINGS ,[object Object],[object Object],[object Object]

MIXED SIGNAL LAYOUT ISSUES SHIELDING Whenever low-level signal line crosses high speed digital line : ,[object Object],[object Object],[object Object],[object Object]

MIXED SIGNAL LAYOUT ISSUES SHIELDING CONTD. ,[object Object],[object Object]

MIXED SIGNAL LAYOUT ISSUES OTHER INTERCONNECT CONSIDERATIONS ,[object Object],[object Object],[object Object],[object Object],[object Object]

Amvdd Data Converter Fundamentals

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Amvdd Data Converter Fundamentals