1. Constrained-Random Thoughts on Design and
Verification of Advanced DSP Blocks for Next-
Generation Handsets
Eric Aardoom, Verification Team Lead, MediaTek Wireless, Inc.
eric.aardoom@mediatek.com
Copyright © MediaTek Inc. All rights reserved.

2. Overview
▪ Our Team
– Who are we and what are we working on?
▪ Our Design and Verification Flow
– The “obvious but traditional” way
– The “new and improved” way
▪ Conclusions
Copyright © MediaTek Inc. All rights reserved. 4/10/2008 2

3. Who Are We?
▪ MediaTek Wireless, RF & Wireless Systems (RFWS):
Cellular handset business of Analog Devices, which
was acquired by MediaTek in January ‘08.
– Provider of chipset solution for 2G/3G handsets, including
GSM/GPRS, EDGE, WCDMA, TD-SCDMA
▪ MediaTek is a fabless semiconductor provider with
headquarters in Taiwan
Copyright © MediaTek Inc. All rights reserved. 4/10/2008 3

4. What are we working on?
3GPP
LTE
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5. Next-Generation Handsets
▪ Powerful application processors and memory
technologies enable advanced applications ….
– “The Internet on your phone”: Productivity apps, Multimedia,
Location services, Games, VOIP, …
▪ But this requires lots of bandwidth …
▪ And to provide this bandwidth wirelessly, physical layer
processing for 3G and beyond is exponentially more
complex than 2/2.5G technologies
– Conventional programmable DSPs have run out of steam
– Requires hardware acceleration for key modem blocks: RAKE,
equalizer, filters, MIMO, H-ARQ, turbo/Viterbi decoders, …
Copyright © MediaTek Inc. All rights reserved. 4/10/2008 5

6. Modem Technology for Next-Generation
Handsets
▪ Othello Radio Technology
– GSM/EDGE
– WCDMA, TD-SCDMA
▪ Analog/Mixed-Signal Baseband
(ABB) Technology
– Integrated Audio/Power
Management
▪ SoftFone Baseband Architecture
– Multi-core (MCU/DSP)
– Modem accelerators for
GSM/GPRS, EDGE, WCDMA,
TD-SCDMA
▪ System-in-Package (SIP) and
System-on-Chip (SoC)
integration
▪ Software, Tools, Support
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7. Solution Design Flow
Radio Access Capabilities
•Standard (R99,R4, HSDPA/HSUPA)
•Uplink/downlink capability, category
Algorithm studies
Verify/validate •Performance envelopes
Not good •Fixed-point optimization
Architecture study
Verify/validate •HW/SW partition
•Accelerator architecture
Crisis
Detailed design
Verify/validate RTL coding
Firmware coding
Catastrophe
Verify/validate P&R, fab, integration
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8. Algorithms: Verifying/Validating Link-Level
Models
64kbps, static channel 64kbps, channel case 1
15 0 3GPP Req. -1
10 3GPP Sim. 10
SYPS Turbo
1-10: active
BLER
ADI Turbo
BLER
-2
10
10 -2
10
Desired Threshold
0 1 2 10 15 20
64kbps, channel case 2 64kbps, channel case 3
5 10
-1
11-16: inactive -1
10
BLER
BLER
-2
10
0 -2 -3
2 4 6 8 10 12 14 16 10 10
6 8 10 12 4 6 8 10 12
I /I (dB) I /I (dB)
or oc or oc
Transmission Parameters Receiver algorithms
•Error-Correction Coding •Channel estimation
•Rate-matching •Demodulation
•Modulation •Detection
•Spreading •Quantization effects
Environment Parameters Key Performance Indicators
•Channel conditions (multi-path •Block Error Rate (BLER)
fading profile, SINR) •Effective throughput
Copyright © MediaTek Inc. All rights reserved. 4/10/2008 8

9. Architecture: HW/SW Partitioning
▪ Start from DSP executable
– MIPS, memory, power
▪ Assign to HW
– Cycle budget busters
– Regular structures
There is more to HW/SW partition
than raw performance– Mature algorithms
– Short/long word lengths
▪ Assign to SW
– Light workloads
– New standards
– Standard word length (16,
ConsV MF ACD 32 bits)
ConsA Fact Subst – 3rd party IP
Copyright © MediaTek Inc. All rights reserved. 4/10/2008 9

10. Verification: The Obvious but Traditional Way
64kbps, static channel 64kbps, channel case 1
15 0 3GPP Req. -1
10 3GPP Sim. 10
1-10: active SYPS Turbo
BLER
ADI Turbo
BLER
-2
10
10 -2
10
Desired Threshold
0 1 2 10 15 20
64kbps, channel case 2 64kbps, channel case 3
5 -1
10
11-16: inactive -1
10
BLER
BLER
-2
10
0 -2 -3
2 4 6 8 10 12 14 16 10 10
6 8 10 12 4 6 8 10 12
I /I (dB) I /I (dB)
or oc or oc
Environment
And Device Golden vectors
Configuration
RTL Testbench
BFM
DUV Checker
BFM
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11. Device Configuration Parameters (TrCH,
CCTrCH)
aim1 , aim 2 , aim 3 ,K, aimAi
CRC attachment
▪ CRC size
bim1 , bim 2 , bim 3 ,K, bimBi
TrBk concatenation /
Code block segmentation ▪ Transport block size, number of
oir1 , oir 2 , oir 3 ,K , oirKi
Channel coding
1..N TrCH transport blocks
ci1 , ci 2 , ci 3 ,K , ciEi
Radio frame equalisation ▪ Channel coding: Turbo,
ti1 , ti 2 , ti 3 ,K, tiTi
1st interleaving
convolutional (rate-½, 1/3)
d i1 , d i 2 , d i 3 ,K, diTi
Transmit Time Interval (TTI)
Radio frame segmentation
ei1 , ei 2 , ei 3 ,K, eiN i
Legal configuration ▪space is huge
Rate matching
Rate
matching ▪ Rate matching parameter
f i1 , f i 2 , f i 3 ,K, f iVi
TrCH Multiplexing
h1 , h2 , h3 , K, hS
Bit Scrambling 1..M CCTrCH •Physical Channel parameters
s1 , s2 , s3 ,K, sS
Physical channel
•Timeslot
•Slot format
segmentation
u p1 , u p 2 , u p 3 , K , u pU p
2nd interleaving
vt ,1 , vt , 2 , vt ,3 ,K , vt ,U t •UE codes
Subframe segmentation
g p1 , g p 2 , g p 3 , K, g pU p
Physical channel mapping
w p1 , w p 2 , w p 3 , K , w pU p
Source: 3GPP TS25.222
PhCH#1
PhCH#2
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12. Problems with the Obvious Way
▪ Full coverage requires massive amounts of vectors
▪ Verification environment is static, can’t react to DUV
▪ High-level environment and device configuration
parameters are lost
▪ Link-level environment is usually not set up for complex
and non-typical scenarios
▪ Not all device behaviors fully modeled in link-level
environment
▪ Your system team will end up hating you!
Copyright © MediaTek Inc. All rights reserved. 4/10/2008 12

13. Verification: The New and Improved Way
▪ SystemVerilog
– Big step up from verilog
▪ Stimulus
– Directed vectors (compliance, bring-up)
– Constrained-random scenarios (coverage-driven)
– Embedded transmitter models (DPI)
▪ Checking
– Data checking with embedded reference models (DPI)
– Protocol checking with monitors/assertions
▪ Coverage
– Code coverage
– Functional coverage
• Cover properties (embedded in RTL)
• Covergroups (embedded in testbench, automatically generated from XML
register database)
Copyright © MediaTek Inc. All rights reserved. 4/10/2008 13

14. Constrained-Random Verification
Environment
Environment
Test And Device
scenarios Configuration
Scoreboard
Generator Receiver
model
Coverage
Transmitter/ MON MON database
Environment
Model
BFM
DUV BFM
BFM
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15. HSDPA Device Configuration Parameters (HS-
DSCH)
// Ki = code block size
•Transport block size
aim1 ,aim2 ,aim3 ,...aimA
// Ci = number of code blocks
CRC attachment
bim1 ,bim2 ,bim3 ,...bimB
// Fi = number of filler bits
// Z = max. code block size
•Rate-matching parameters
Code block segmentation
// Yi = encoded data size •Modulation type
constraint xxx_constraint {
oir1 ,oir2 ,oir3,...oirK Z == 5114; •Constellation version
Channel Coding
Use constraints to Fi
// Equations for compute
•Spreading factor
Fi inside {[0:39]};
derived parameters,<define
ci1,ci2,ci3,...ciE //(Xi >= 40) -> (Fi Ci); •Active physical channels
interesting testcases
// Equations for Ci
Physical Layer Hybrid-ARQ
functionality Ci inside {[1:3]}; •Active timeslots
w1,w2,w3,...wR
•Encoder/decoder filler bits
Ci * Z >= Xi;
Ci * Z < Xi + Z;
Bit Scrambling
•Code FiEquations forKi;
+ Xi == Ci *
block size Yi
//
s1,s2,s3,...sR
Yi == (3 * Ki + 12);
Interleaving•Number Ci == N1;
Yi * of code blocks
HS-DSCH
// Equations for Ki
v1 ,v2 ,v3 ,...vR
Ki <= Z;
Constellation
re-arrangement
Ki * Ci >= Xi;
for 16 QAM Ki * Ci < Xi + Ci;
r1 ,r2 ,r3 ,...rR //(Xi < 40) -> Ki == 40;
}
Physical channel mapping
wt,p,1,wt,p,2,…wt,p,Up Source: 3GPP TS25.222
PhCH#1 PhCH#P
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16. Result: Bug Tracking for a “reused” IP
▪ RTL was reused in different
configuration
▪ Model was adapted to TDD
standard
▪ Testbench was “borrowed”
from previous project
▪ Week 1: Designer testbench
▪ Week 2-3: Directed
▪ Week 4-8: Random+directed
▪ Week 9-13: Constrained-
1 3 5 7 9 11 13
random
RTL Model Testbench
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17. Executable reference models are key !
“Known-good”
point of reference
Architect
RTL Designer/ System
DV Engineer Engineer
▪ No ambiguities: Architect, RTL/DV Engineer and System
Engineer all use the same golden reference model
– Eliminates guesswork of interpreting written specifications
– Eliminates rework by reusing system model for RTL/DV and system
integration
Copyright © MediaTek Inc. All rights reserved. 4/10/2008 17

18. Conclusions
▪ Next-generation handsets have sophisticated DSP
acceleration that gets progressively harder to verify
▪ Don’t use your system team as a generator of infinite
stream of testcases, but as a source of high quality
reference models
▪ Build constrained-random verification environment
incorporating reference models for testcase generation
and data checking
▪ We’ve successfully taped out 2 chips with this
methodology (the first is in production, the second
under customer eval)
Copyright © MediaTek Inc. All rights reserved. 4/10/2008 18

19. www.mediatek.com
Copyright © MediaTek Inc. All rights reserved.