4. Microprocessor Basic Microprocessor, by-itself, completely useless – must have external peripherals to Interact with outside world CPU CONTROL ADDRESS DATA BOOT ROM Used at startup Instruction (program) ROM Transducers Keyboard Screen UART Parallel interface etc Data RAM
17. Traditional embedded system design using DSP Power Supply CLK CLK CLK custom IF-logic SDRAM SDRAM SRAM SRAM SRAM Memory Controller UART LC Display Controller Interrupt Controller Timer Audio Codec CPU (uP / DSP) Co- Proc. GP I/O Address Decode Unit Ethernet MAC
18. Next Step... CLK custom IF-logic Memory Controller UART Display Controller Timer CPU (uP / DSP) Co- Proc. GP I/O Address Decode Unit Ethernet MAC Interrupt Controller FPGA CLK CLK SDRAM SDRAM SRAM SRAM SRAM Power Supply LC Audio Codec
19. Configurable system on Chip-CSoC Power Supply SDRAM SDRAM SRAM SRAM SRAM LC Audio Codec EPROM
20.
21. SMP-BF561 • Identical Cores • Identical access to all System Resources • Memory, Disk, UARTs, Communication Controllers, • Examples: Analog Devices Blackfin 561
28. Software Design Flow -FPGA Generate Netlist ISE Platform Ext. Proj.Nav. / VHDL *.mhs *. elf *.c *.asm Compile & Link Update Bitstream *. bit *.h Gen. Libs Platform Definition (peripherals, configuration, connectivity, address space) EDK: Embedded Development Kit XPS: Xilinx Platform Studio ISE: Integrated Software Environment MHS: Microprocessor Hardware Specification *. bit XPS Generate Bitstream *.ucf Hardware Software *.bmm
29. RTOS, Board Support Package Integrated HW/SW/FPGA Flows Instantiate the ‘ System Netlist’ and Implement the FPGA Include the BSP and Compile the Software Image 1 2 3 Xilinx Platform Studio SDK Xilinx Platform Studio Data2MEM Download Combined Image to FPGA Compiled ELF Compiled BIT Embedded Development Kit ? HDL Entry Simulation/Synthesis Implementation Download Bitstream Into FPGA Chipscope Standard FPGA HW Development Flow VHDL or Verilog System Netlist ? Code Entry C/C++ Cross Compiler Linker Load Software Into FLASH Debugger Standard Embedded SW Development Flow C Code Board Support Package Compiled BIT Compiled ELF
32. Unified Tool Releases, All Tools Available for Evaluations Verilog VHDL C/C++ MATLAB Simulink 3 rd Party Unified Design Environment The Ultimate System Integration Design Tools New ! HW Designers SW Developers Architects Verification Team System Integrators . . . .
33. Design Decision in Choosing an FPGA Programmable technology Gate count Number of I/O’S Manufacturer Family Device Power Consumption Speed,voltage Packaging