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Interrupt system f28x

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This ppt will help you to know more about interrupt and pie block interrupt , and how to use pie interrupt. All the needed registers are explained briefly.

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Interrupt system f28x

  1. 1. Chapter 4 : Interrupt System C28x Digital Signal Controller TMS320F2812Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  2. 2. RS C28x Core Interrupt Lines NMI INT1 INT2 • 2 non-maskable interrupts (RS, INT3 INT4 “selectable” NMI) C28x INT5 • 14 maskable interrupts (INT1 – INT6 CORE INT7 INT14) INT8 INT9 INT10 INT11 INT12 INT13 INT14Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  3. 3. C28x Reset Sources C28x Core Watchdog Timer RS RS pin active To RS pinTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  4. 4. Register Bits Initialized at Reset Register bits defined by reset PC 0x3F FFC0 PC loaded with reset vector ACC 0x0000 0000 Accumulator cleared XAR0 - XAR7 0x0000 0000 Auxiliary Registers DP 0x0000 Data Page pointer points to page 0 P 0x0000 0000 P register cleared XT 0x0000 0000 XT register cleared SP 0x0400 Stack Pointer to address 0400 RPC 0x00 0000 Return Program Counter cleared IFR 0x0000 no pending interrupts IER 0x0000 maskable interrupts disabled DBGIER 0x0000 debug interrupts disabledTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  5. 5. Control Bits Initialized at Reset Status Register 0 (ST0) SXM = 0 Sign extension off OVM = 0 Overflow mode off N=0 negative flag TC = 0 test/control flag V=0 overflow bit C=0 carry bit PM = 000 set to left-shift-by-1 Z=0 zero flag OVC = 00 0000 overflow counter Status Register 1 (ST1) INTM = 1 Disable all maskable interrupts - global DBGM = 1 Emulation access/events disabled PAGE0 = 0 Stack addressing mode enabled/Direct addressing disabled VMAP = 1 Interrupt vectors mapped to PM 0x3F FFC0 – 0x3F FFFF SPA = 0 stack pointer even address alignment status bit LOOP = 0 Loop instruction status bit EALLOW = 0 emulation access enable bit IDLESTAT = 0 Idle instruction status bit AMODE = 0 C27x/C28x addressing mode OBJMODE = 0 C27x object mode M0M1MAP = 1 mapping mode bit XF = 0 XF status bit ARP = 0 ARP points to AR0Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  6. 6. Reset – Bootloader XMPNMC=1 Reset (microprocessor mode) Reset vector fetched OBJMODE=0 AMODE=0 from XINTF zone 7 ENPIE=0 VMAP=1 0x3F FFC0 M0M1MAP=1 XMPNMC=0 (microcomputer mode) Reset vector fetched from boot ROM Boot determined by state of GPIO pins 0x3F FFC0 Notes: Execution Bootloading Entry Point Routines F2810 XMPNMC tied low internal to device FLASH SPI XMPNMC refers to input signal H0 SARAM SCI-A MP/MC is status bit in XINTFCNF2 register OTP Parallel load XMPNMC only sampled at resetTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  7. 7. Bootloader Options GPIO pins F4 F12 F3 F2 1 x x x jump to FLASH address 0x3F 7FF6 * 0 0 1 0 jump to H0 SARAM address 0x3F 8000 * 0 0 0 1 jump to OTP address 0x3D 7800 * 0 1 x x bootload external EEPROM to on-chip memory via SPI port 0 0 1 1 bootload code to on-chip memory via SCI-A port 0 0 0 0 bootload code to on-chip memory via GPIO port B (parallel) * Boot ROM software configures the device for C28x mode before jumpTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  8. 8. Reset Code Flow - Summary 0x3D 7800 OTP (2K) 0x3D 8000 FLASH (128K) 0x3F 7FF6 0x3F 8000 H0 SARAM (8K) Execution Entry 0x3F F000 Boot ROM (4K) Point Determined Boot Code By GPIO Pins 0x3F FC00 • • • • BROM vector (32) RESET 0x3F FFC0 0x3F FC00 Bootloading Routines (SPI, SCI-A, Parallel Load)Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  9. 9. Internal Sources Interrupt Sources TINT2 TINT1 C28x CORE TINT0 RS NMI EV and Non-EV PIE Peripherals INT1 (Peripheral (EV, ADC, SPI, Interrupt INT2 SCI, McBSP, CAN) Expansion) INT3 • External Sources • • INT12 XINT1 INT13 XINT2 INT14 PDPINTx RS XNMI_XINT13Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  10. 10. Maskable Interrupt Processing Conceptual Core Core (IFR) (IER) (INTM) Interrupt “Latch” “Switch” “Global Switch” INT1 1 INT2 0 C28x Core INT14 1  A valid signal on a specific interrupt line causes the latch to display a “1” in the appropriate bit  If the individual and global switches are turned “on” the interrupt reaches the coreTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  11. 11. Interrupt Flag Register (IFR) 15 14 13 12 11 10 9 8 RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9 7 6 5 4 3 2 1 0 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 Pending : IFR Bit = 1 Absent : IFR Bit = 0 /*** Manual setting/clearing IFR ***/ extern cregister volatile unsigned int IFR; IFR |= 0x0008; //set INT4 in IFR IFR &= 0xFFF7; //clear INT4 in IFR Compiler generates atomic instructions (non-interruptible) for setting/clearing IFR  If interrupt occurs when writing IFR, interrupt has priority  IFR(bit) cleared when interrupt is acknowledged by CPU  Register cleared on resetTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  12. 12. 15 Interrupt Enable Register (IER) 14 13 12 11 10 9 8 RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9 7 6 5 4 3 2 1 0 INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1 Enable: Set IER Bit = 1 Disable: Clear IER Bit = 0 /*** Interrupt Enable Register ***/ extern cregister volatile unsigned int IER; IER |= 0x0008; //enable INT4 in IER IER &= 0xFFF7; //disable INT4 in IER  Compiler generates atomic instructions (non-interruptible) for setting/clearing IER  Register cleared on resetTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  13. 13. Interrupt Global Mask Bit Bit 0 ST1 INTM • INTM used to globally enable/disable interrupts: – Enable: INTM = 0 – Disable: INTM = 1 (reset value) • INTM modified from assembly code only: /*** Global Interrupts ***/ asm(“ CLRC INTM”); //enable global interrupts asm(“ SETC INTM”); //disable global interruptsTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  14. 14. Peripheral Interrupt Expansion - PIE Interrupt Group 1 PIE module for 96 Interrupts PIEIFR1 PIEIER1 INT1.x interrupt group INT1.1 1 INT2.x interrupt group INT1.2 0 INT3.x interrupt group INT1 • • INT4.x interrupt group • • INT5.x interrupt group • • INT1.8 1 INT6.x interrupt group 96 INT7.x interrupt group 28x Core Interrupt logic INT8.x interrupt group INT9.x interrupt group INT1 – INT 12 28x INTM INT10.x interrupt group IER IFR 12 Interrupts INT11.x interrupt group Core r e n l ar e hp r e P INT12.x interrupt group i INT13 (TINT1 / XINT13) INT14 (TINT2) NMI t ITechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  15. 15. PIE Registers PIEIFRx register (x = 1 to 12) 15 - 8 7 6 5 4 3 2 1 0 reserved INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 PIEIERx register (x = 1 to 12) 15 - 8 7 6 5 4 3 2 1 0 reserved INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 PIE Interrupt Acknowledge Register (PIEACK) 15 - 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved PIEACKx PIECTRL register 15 - 1 0 PIEVECT ENPIE #include “DSP28_Device.h” PieCtrlRegs.PIEIFR1.bit.INTx4 = 1; //manually set IFR for XINT1 in PIE group 1 PieCtrlRegs.PIEIER3.bit.INTx5 = 1; //enable CAPINT1 in PIE group 3 PieCtrlRegs.PIEACK.all = 0x0004; //acknowledge the PIE group 3Technology beyond the Dreams™ = 1; //enable the PIE Copyright © 2006 Pantech Solutions Pvt PieCtrlRegs.PIECTRL.bit.ENPIE
  16. 16. Default Interrupt Vector Table at Reset Prio Vector Offset 1 Reset 00 Default Vector Table 5 Int 1 02 Remapped when 6 Int 2 04 ENPIE = 1 7 Int 3 06 Memory 8 Int 4 08 0 9 Int 5 0A 10 Int 6 0C 11 Int 7 0E 12 13 Int 8 10 0x00 0D00 14 Int 9 12 Int 10 PIE Vectors 15 14 256 W 16 Int 11 16 17 Int 12 18 18 Int 13 1A 19 Int 14 1C 0x3F FFC0 BROM Vectors DlogInt 1E 64 W 4 RtosInt 20 0x3F FFFF 2 EmuInt 22 3 NMI 24 PIE vector generated by config Tool - Illegal 26 Used to initialize PIE vectors - User 1-12 28-3ETechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  17. 17. PIE Vector Mapping (ENPIE Vector name PIE vector address PIE vector Descriptiont used 0x00 0D00 Reset Vector Never Fetched Here = 1) INT1 0x00 0D02 INT1 re-mapped below …… …… …… re-mapped below INT12 0x00 0D18 INT12 re-mapped below INT13 0x00 0D1A XINT1 Interrupt Vector INT14 0x00 0D1C Timer2 – RTOS Vector Datalog 0x00 0D1D Data logging vector …… …… …… USER11 0x00 0D3E User defined TRAP INT1.1 0x00 0D40 PIEINT1.1 interrupt vector …… …… ……INT1.8 0x00 0D4E PIEINT1.8 interrupt vector …… …… ……INT12.1 0x00 0DF0 PIEINT12.1 interrupt vector …… …… ……INT12.8 0x00 0DFE PIEINT12.8 interrupt vector  PIE vector space - 0x00 0D00 – 256 Word memory in Data space  RESET and INT1-INT12 vector locations are Re-mappedTechnology beyond are remapped to 0x00 0D00 in Data space © 2006 Pantech Solutions Pvt  CPU vectors the Dreams™ Copyright
  18. 18. INT1 F2812/10 PIE Interrupt INTx.8 WAKEINT INTx.7 TINT0 INTx.6 ADCINT INTx.5 XINT2 INTx.4 XINT1 INTx.3 INTx.2 PDPINTB INTx.1 PDPINTA INT2 Assignment Table T1OFINT T1UFINT T1CINT T1PINT CMP3INT CMP2INT CMP1INT INT3 CAPINT3 CAPINT2 CAPINT1 T2OFINT T2UFINT T2CINT T2PINT INT4 T3OFINT T3UFINT T3CINT T3PINT CMP6INT CMP5INT CMP4INT INT5 CAPINT6 CAPINT5 CAPINT4 T4OFINT T4UFINT T4CINT T4PINT INT6 MXINT MRINT SPITXINTA SPIRXINTA INT7 INT8 INT9 ECAN1INT ECAN0INT SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA INT10 INT11 INT12Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  19. 19. _int00 > F FFCO> = Boot-ROM Code F FFCO> = Boot-ROM Code F 7FF6 > = LB _c_int00 F 7FF6 > = LB _c_int00 hip ROM memory) hip ROM memory) int00 > Device Vector Mapping - Summary RESET MPNMC = 1 (external memory XINTF) MPNMC = 1 (external memory XINTF) User Code Start < _c_int00> Reset Vector <0x3F FFCO> = _c_int00 Reset Vector <0x3F FFCO> = _c_int00 _c_int00: . . . CALL main() Initialization ( ) { EALLOW main() Load PIE Vectors PIE Vector Table { initialization(); Enable the PIEIER 256 Word RAM . . . Enable PIECTRL Enable Core IER 0x00 0D00 – 0DFF } Enable INTM EDIS }Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  20. 20. Interrupt Response - Hardware Sequence CPU Action Description Registers → stack 14 Register words auto saved 0 → IFR (bit) Clear corresponding IFR bit 0 → IER (bit) Clear corresponding IER bit 1 → INTM/DBGM Disable global ints/debug events Vector → PC Loads PC with int vector address Clear other status bits Clear LOOP, EALLOW, IDLESTAT Note: some actions occur simultaneously, none are interruptible T ST0 AH AL PH PL AR1 AR0 DP ST1 DBSTAT IER PC(msw) PC(lsw)Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  21. 21. Latency ext. interrupt occurs Interrupt Latency Internal interrupt occurs Assumes ISR in internal RAM here here cycles 2 4 3 3 1 3 Recognition Get vector ISR Sync ext. PF1/PF2/D1 Save D2/R1/R2 of instruction signal delay (3) and (3 reg. of ISR return ISR executed on SP alignment pairs instruction address instruction (ext. interrupt (1) saved) next cycle (3 reg. pairs only) saved) Above is for PIE enabled or disabled  Minimum latency (to when real work occurs in the ISR):  Internal interrupts: 14 cycles  External interrupts: 16 cycles  Maximum latency: Depends on wait states, ready, INTM, etc.Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  22. 22. C28x CPU Timers RESET Timer Reload 16 - Bit divide down 32 - Bit period TDDRH:TDDR PRDH:PRD SYSCLKOUT 16 - Bit prescaler 32 - Bit counter PSCH:PSC TIMH:TIM TCR.4 BORROW INTTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  23. 23. C28x Timer Interrupt System PIE unit TINT0 INT1.7 interrupt 28x Core Interrupt logic INT1 TINT1 / XINT13 INT13 28x INTM IER IFR Core INT14 TINT2Technology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  24. 24. C28x Timer Registers Address Register Name 0x0000 0C00 TIMER0TIM Timer 0, Counter Register Low 0x0000 0C01 TIMER0TIMH Timer 0, Counter Register High 0x0000 0C02 TIMER0PRD Timer 0, Period Register Low 0x0000 0C03 TIMER0PRDH Timer 0, Period Register High 0x0000 0C04 TIMER0TCR Timer 0, Control Register 0x0000 0C06 TIMER0TPR Timer 0, Prescaler Register 0x0000 0C07 TIMER0TPRH Timer 0, Prescaler Register High 0x0000 0C08 TIMER1TIM Timer 1, Counter Register Low 0x0000 0C09 TIMER1TIMH Timer 1, Counter Register High 0x0000 0C0A TIMER1PRD Timer 1, Period Register Low 0x0000 0C0B TIMER1PRDH Timer 1, Period Register High 0x0000 0C0C TIMER1TCR Timer 1, Control Register 0x0000 0C0D TIMER1TPR Timer 1, Prescaler Register 0x0000 0C0F TIMER1TPRH Timer 1, Prescaler Register High 0x0000 0C10 to 0C17 Timer 2 Registers ; same layout as aboveTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt
  25. 25. C28x Timer Control Registers TIMERxTCR Emulator Interaction Timer Interrupt Flag Timer Interrupt Enable 1x = run free Write 1 clear bit Write 1 to enable INT 15 14 13 12 11 10 9 8 TIF TIE reserved reserved FREE SOFT reserved reserved 7 6 5 4 3 2 1 0 reserved reserved TRB TSS reserved reserved reserved reserved Timer Reload Bit Timer Stop Status 1 = reload 0 = start / 1 = stopTechnology beyond the Dreams™ Copyright © 2006 Pantech Solutions Pvt

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