1. ATPG of Reversible Circuits
Rahul Krishnamurthy
Under the Guidance of
Prof.G.K.Sharma
April 20, 2012

2. outline
OUTLINE
◮
Integer Linear programming for ATPG.
◮
Circuit Decomposition Approach to generate test patterns.
◮
SAT based ATPG for Reversible Circuits.

3. BASICS
Complete and minimal test sets
◮
Given a reversible circuit C and a fault set F ,a set of test
vectors that detect all faults in F is called a complete test set.
◮
A complete test set with the fewest possible vectors is minimal

4. BASICS
Observability and Controllabilty
Observability and Controllabilty
Two important properties of reversiblity simplify the test set
generation problem.
◮
Controllability: There is a test vector that generates any given
desired state on the wires at any given level
◮
Observability: Any single fault that changes an intermediate
state in the circuit also changes the output

5. ILP Formulation for ATPG
Basic ILP terminology
◮
i th Input Vector is denoted by Ti
◮
Each Ti associated by a binary decision variable ti .
◮
ti → one if the corresponding input vector is in the test set.
◮
ti → zero if the corresponding input vector is not in the test
set.
◮
A fault is detected if a decision variable with value one
corresponds to a vector that detects the fault.

6. ILP Formulation for ATPG
ILP model
ILP Model
level 0
◮
level 1
level 2
The values of the wires at the j th level for input Ti are
fj (Ti )
◮
To detect all stuck-at 0 faults at level j the following
inequalities must be satisfied
2n −1
i =0 fj (Ti )xti
◮
≥1
The above inequality guarantee that each value at the j th
level is set to 1 by some test vector ensuring that all stuck-at
0 faults are detected

7. ILP Formulation for ATPG
ILP model
ILP Model contd..
◮
A similar set of inequalities ensures that all stuck-at 1 faults
are also detected.
◮
Total 2n(d+1) linear inequality constarints are used to
guarantee completeness.
◮
n denotes the number of lines and d is the number of levels.

8. ILP Formulation for ATPG
ILP model contd..
ILP model contd..
◮
There are 3 lines and a total of 3 levels So for stuck-at 0 a
total of 3x3 constriants are there.
◮
There are 3 lines and a total of 3 levels So for stuck-at 1 a
total of 3x3 constriants are there.
◮
Total linear inequality constarints are 18 .

9. ILP formulation
ILP formulation
◮
The general ILP formulation of the minimal test-set problem
for a reversible circuit on n wires and with depth d is:
MINIMIZE t0 + t1 + t2 + t3 + t4 + · · · + t2n −1
subject to constraints
2n −1
i =0 fj (Ti ).ti
≥1
2n −1
i =0 fj (Ti ).ti
≥1
for all 0 ≤ j ≤ d
where ti ∈ {0, 1}, andTi is the n-bit binary expansion of
integer i

10. ILP formulation
example
Example
level 0
level 1
level 2
0
0
0
0
0
0
0
0
0
0
0
1
0
level 0
0
level 1
level 2
level 0
level 0
level 1
1
level 1
level 2
0
0
1
level 2
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
0

11. ILP formulation
Example contd..
Example Contd..
The following inequalities guarantees that each of the fault sites
can be set to 1.
0 0 0 0 1 1 1 1
7
 t0 
i =0 f0 (Ti ).ti ≥ 1
00110011
t1
0 1 0 1 0 1 0 1
7
 t2  ≥ 1
0 0 0 0 1 1 1 1 ·

 t3 
i =0 f1 (Ti ).ti ≥ 1 ⇐⇒
0 0 1 1 1 1 0 0
 t4 
0 1 0 1 0 1 0 1
7
t5
00001111
i =0 f2 (Ti ).ti ≥ 1
t6
00111100
01101001
t7

12. ILP formulation
Example contd..
Example Contd..
The following inequalities guarantees that each of the fault sites
can be set to 0.
1 1 1 1 0 0 0 0
7
 t0 
i =0 f0 (Ti ).ti ≥ 1
11001100
t1
1 0 1 0 1 0 1 0

7
 t2  ≥ 1
1 1 1 1 0 0 0 0 ·
 t3 
i =0 f1 (Ti ).ti ≥ 1 ⇐⇒
1 1 0 0 0 0 1 1
 t4 
1 0 1 0 1 0 1 0
7
t5
11110000
t6
i =0 f2 (Ti ).ti ≥ 1
11000011
10010110
t7
◮
Solving ILP , gives three test vectors to detect all stuck-at
faults in the circuit
◮
One such solution is t0 = t7 = t2 = 1

13. ILP Limitations
ILP Limitation
◮
The number of variables increases exponentially with number
of input/output bits.
◮
ILP method is feasible for small circuits.It is impractical for
large circuits.
◮
An alternative approach is to decompose the original circuit
into smaller sucircuits
◮
Use ILP formulation iteratively for these subcircuits.

14. Circuit-Decomposition Approach
Circuit-Decomposition Approach
◮
The circuit is first decomposed into a series of circuits acting
on small number of wires.
◮
◮
Start at the input of the circuit and add gates to the first
subcircuit C0 .
Keep adding until no more can be added without having C0
act on more than m wires.

15. Circuit-Decomposition Approach
Example
Example
X0
X1
X2
X3
X4
X5
C0
C1
C2
◮
The entire circuit acts on six wires.
◮
Each subcircuit acts on no more than 4 wires.

16. Circuit-Decomposition Approach
Example contd..
◮
ILP is performed on the subcircuit C0 which provides following
test vectors
v0 =
v1 =
v2 =
x0
X
X
X
x1
0
1
1
x2
1
0
1
x3
X
X
X
x4
1
0
1
x5
1
0
0
C
→
−0
x0
X
X
X
x1
1
1
0
x2
1
0
0
x3
X
X
X
x4
0
1
1
◮
These 3 test vectors forms complete test set for Stuck-at
faults in the C0
◮
Left and right halves represent the test vectors at the input
and output of C0 respectively
x5
0
0
1

17. Circuit-Decomposition Approach
Example contd
◮
◮
=⇒
◮
◮
Subcircuit C1 acts on wires x0 , x1 , x4 andx5
At the input of C1 the output of C0 is applied.
x0
X
X
X
x1
1
1
0
x4
0
1
1
x5
0
0
1
∈T
From above x0 can be either 0 or 1
For both the cases test vectors becomes
x0
0
0
0
x1
1
1
0
x4
0
1
1
x5
0
0
1
x0
1
1
1
x1
1
1
0
x4
0
1
1
x5
0
0
1

18. Circuit-Decomposition Approach
Example contd
◮
We generate the ILP for C1 add the following constraints
CONSTRAINTS
t4 + t12 ≥ 1
t6 + t14 ≥ 1
t3 + t11 ≥ 1
◮
Solving ILP gives the solution t6 = t11 = t12 = 1
◮
These values will be Incorporated into the the previous test
vectors.

19. Circuit-Decomposition Approach
Example contd
◮
Left and right halves represent the test vectors at the input
and output of C1 respectively
x0
1
0
1
x1
1
1
0
x2
1
0
0
x3
X
X
X
x4
0
1
1
x5
0
0
1
C
→
−1
x0
0
1
1
x1
1
1
0
x2
1
0
0
x3
X
X
X
x4
0
1
1
x5
0
0
1

20. Circuit-Decomposition Approach
Example contd
◮
Subcircuit C2 acts on wires x0 , x1 , x2 andx3
◮
Generate the ILP for this circuit and incorporate the current
test set using the following constraints:
x0
0
1
1
x1
1
1
0
x2
1
0
0
x3
X
X
X
∈ T =⇒
CONSTRAINTS
t6
+ t7
≥ 1
t12 + t13 ≥ 1
t8
+ t9
≥ 1
◮
Solving this ILP gives solutions t5 , t7 , t8 andt12
◮
The last three can be incorporated into the previous test set
however the first test vector must be added as in

21. Circuit-Decomposition Approach
Example contd
x0
0
1
1
0
◮
x1
1
1
0
1
x2
1
0
0
0
x3
1
0
0
1
x4
0
1
1
X
x5
0
0
1
X
=⇒
x0
0
0
1
1
x1
1
1
1
0
x2
1
0
0
0
x3
0
0
0
1
x4
0
1
1
X
x5
0
0
1
X
Filling the don’t cares with 0’s and applying C −1 to the test
set yields a complete test set for C.

22. SAT
SAT
◮
◮
The SAT problem is defined as follows:
Let h be a Boolean function in Conjunctive normal form i.e
product-of-sum repesentation.
◮
example : h = (x1 + x2 + x3 )(x1 + x3 )(x2 + x3 )
◮
Then the SAT problem is to determine an assignment for the
variable h so that h evaluates to 1 or to prove that no such
assignment exists
◮
For the above example x1 = 1, x2 = 1 and x3 = 1 is a
satisfying assignement for h.
◮
The values of x1 and x2 ensures that the first clause become
satisfied while x3 ensures this for the remaining two clauses

23. SAT Based ATPG
SAT Based ATPG terminology
◮
Let a G be circuit with n lines and d gates then
◮
◮
◮
→
1 1
1
Variable − 1 = xn , xn−1 · · · x1 represents the assignement to
x
the respective input lines of the circuit
→
Variable − d+1 = x d+1 , x d+1 · · · x d+1 represents the
x
n
n−1
1
assignement to respective output lines of the circuit
→
k k
k
Variable− k = (xn xn−1 · · · x1 ) with 2 ≤ k ≤ d represents the
x
input(output) assignment to the respective lines of the gate
gk (gk−1 )
level 1
level 2
level 3

24. SAT Based ATPG
constraints
Constraints
◮
For every gate gk (Ck , xtk ) in the circuit,the respective
input/output mapping is constraint
◮
Values of all lines (except the target lines)are passed through
i.e (xik+1 = xik )
◮
While the output value for the target line is determined
depending on the input values of the control and the target
line respectively
(xik+1 = xik xor ∧xc∈Ck xc )
◮
After this the constraints are added ensuring that the faulty
behavior is activated .
◮
Example: In the case that a test pattern for an SMCF at the
i th line of gate gk sholud be generated .The constraint :
(xik = 0) ∧ ( xc ∈Ck xc = 1) is added

25. SAT Based ATPG
Additional Constraints
Additional Constraints
◮
Finally the additional constraints are added to the instance .
◮
For example: constant inputs.
◮
i.e for each constant inputs ,constraints have to added
,ensuring that the respective variable xi1 is assigned to the
according value.

26. SAT based ATPG Example
SAT based ATPG Example
1
X
1
1
1
X
2
X
1
3
X
1
4
X
1
2
X
2
3
X
2
4
X
2
2
X
3
3
X
3
4
X
3
2
X
4
3
X
4
4
X
4
2
X
5
3
X
5
4
X
5
2
1
X
3
1
X
4
1
X
5
Functional Constraints:
2
1
2
1
1
x1 = x1 x2 = x2 ⊕ x5
2
1
2
1
x3 = x3 x4 = x4
2 = x1
x5
5
3
2
3
2
x1 = x1 x2 = x2
Additional Constraints:
1
x1 = 1
5
X
1
5
X
2
5
X
3
5
X
4
5
X
5
Fault constraints:
3
x2 = 0
3
x4 = 1
3
x5 = 1

27. SAT based ATPG Example
SAT based ATPG Example
SAT based ATPG Example
◮
The three constraints are converted into CNF -the common
input format of SAT solvers
◮
If the solver then determines a satisfying assignment for the
resulting instance,a valid test pattern can be obtained from
1
1
the assingmnet to x1 · · · xn
◮
If the SAT solver returns unsatisfiable ,then it has been proven
that no test pattern considering the additional constraints
exists- the respective fault is untestable under these
constraints.

28. Conclusion
Conclusion
◮
ILP provides a complete and minimal test patterns
◮
The Ilp formulation is feasible for small circuits;since the
number of variables increses exponentially with the number of
input/output bits
◮
In circuit decomposition technique the test set is not
guaranteed to be minimal.
◮
ATPG SAT is effecient when additional constraints of
Constant inputs is considered.

29. References
References
◮
Ketan N. Patel, John P. Hayes,and Igor L. Markov,“Fault
Testing for Reversible Circuits”,IEEE TRANSACTIONS ON
COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS
AND SYSTEMS, VOL. 23, NO. 8, AUGUST 2004
◮
Hongyan Zhang,Robert Wille and Rolf Drechsle “SAT-based
ATPG for Reversible Circuits”,Design and Test Workshop
(IDT), 2010 5th International , vol., no., pp.149-154, 14-15
Dec. 2010