The document discusses machine instructions and program execution, including different methods for representing signed integers like sign-and-magnitude, one's complement, and two's complement. It also covers binary addition and subtraction using two's complement representation, addressing methods for accessing memory operands, and basic operations on data structures like stacks, queues, lists, and arrays.

1. Chapter 2. Machine
Instructions and
Programs
Computer Organization
Lecture 6

2. Objectives
 Machine instructions and program execution,
including branching and subroutine call and return
operations.
 Number representation and addition/subtraction in
the 2’s-complement system.
 Addressing methods for accessing register and
memory operands.
 Assembly language for representing machine
instructions, data, and programs.
 Program-controlled Input/Output operations.
 Operations on stack, queue, list, linked-list, and
array data structures.

3. Number, Arithmetic
Operations, and
Characters

4. Unsigned Integer
 Consider a n-bit vector of the form:
A = an −1an − 2 an − 3  a0
where ai=0 or 1 for i in [0, n-1].
 This vector can represent positive integer values V =
A in the range 0 to 2n-1, where
n −1 n−2
A=2 an −1 + 2 an − 2 +  + 2 a1 + 2 a0
1 0

5. Signed Integer
3 major representations:
Sign and magnitude
One’s complement
Two’s complement
 Assumptions:
4-bit machine word
16 different values can be represented
Roughly half are positive, half are negative

6. Sign and Magnitude
Representation
-7 +0
-6 1111 0000 +1
1110 0001
-5 +2 +
1101 0010
-4 1100 0011 +3 0 100 = + 4
-3 1011 0100 +4 1 100 = - 4
1010 0101
-2 +5 -
1001 0110
-1 1000 0111 +6
-0 +7
High order bit is sign: 0 = positive (or zero), 1 = negative
Three low order bits is the magnitude: 0 (000) thru 7 (111)
Number range for n bits = +/-2n-1 -1
Two representations for 0

7. One’s Complement
Representation
-0 +0
-1 1111 0000 +1
1110 0001
-2 +2 +
1101 0010
-3 1100 0011 +3 0 100 = + 4
-4 1011 0100 +4 1 011 = - 4
1010 0101
-5 +5 -
1001 0110
-6 1000 0111 +6
-7 +7
 Subtraction implemented by addition & 1's complement
 Still two representations of 0! This causes some problems
 Some complexities in addition

8. Two’s Complement
Representation
-1 +0
-2 1111 0000 +1
1110 0001
-3 +2 +
1101 0010
like 1's comp
except shifted -4 1100 0011 +3 0 100 = + 4
one position
clockwise -5 1011 0100 +4 1 100 = - 4
1010 0101
-6 +5 -
1001 0110
-7 1000 0111 +6
-8 +7
 Only one representation for 0
 One more negative number than positive
number

9. Binary, Signed-Integer
Representations
B V alues represented
Sign and
b3 b2b1b0 magnitude 1' s complement 2' s complement
0 1 1 1 +7 +7 + 7
0 1 1 0 +6 +6 + 6
0 1 0 1 +5 +5 + 5
0 1 0 0 +4 +4 + 4
0 0 1 1 +3 +3 + 3
0 0 1 0 +2 +2 + 2
0 0 0 1 +1 +1 + 1
0 0 0 0 +0 +0 + 0
1 0 0 0 - 0 -7 - 8
1 0 0 1 - 1 -6 - 7
1 0 1 0 - 2 -5 - 6
1 0 1 1 - 3 -4 - 5
1 1 0 0 - 4 -3 - 4
1 1 0 1 - 5 -2 - 3
1 1 1 0 - 6 - 1 - 2
1 1 1 1 - 7 -0 - 1
Figure 2.1. Binary, signed-integer representations.

10. Comparison
 Sign and Magnitude
 Cumbersome addition/subtraction
 Must compare magnitudes to determine sign of
result
 One’s Complement
Simply bit-wise complement
 Two’s Complement
Simply bit-wise complement + 1

11. Addition of Positive Numbers
0 1 0 1
+ 0 + 0 + 1 + 1
0 1 1 10
Carry-out
Figure 2.2. Addition of 1-bit numbers.

12. Addition and Subtraction – Sign
Magnitude
4 0100 -4 1100
result sign bit is the
same as the operands' +3 0011 + (-3) 1011
sign
7 0111 -7 1001
when signs differ, 4 0100 -4 1100
operation is subtract,
sign of result depends -3 1011 +3 0011
on sign of number with
the larger magnitude 1 0001 -1 1111 `

13. Addition and Subtraction – 1’s
Complement
4 0100 -4 1011
+3 0011 + (-3) 1100
7 0111 -7 10111
End around carry 1
1000
4 0100 -4 1011
-3 1100 +3 0011
1 10000 -1 1110
End around carry 1
0001

14. Addition and Subtraction – 1’s
Complement
Why does end-around carry work?
n
Its equivalent to subtracting 2 and adding 1
n n
M - N = M + N = M + (2 - 1 - N) = (M - N) + 2 - 1 (M > N)
n n
-M + (-N) = M + N = (2 - M - 1) + (2 - N - 1) n-1
M+N<2
n n
= 2 + [2 - 1 - (M + N)] - 1
after end around carry:
n
= 2 - 1 - (M + N)
this is the correct form for representing -(M + N) in 1's comp!

15. Addition and Subtraction – 2’s
Complement
4 0100 -4 1100
+3 0011 + (-3) 1101
If carry-in to the high
order bit = 7 0111 -7 11001
carry-out then ignore
carry
if carry-in differs from 4 0100 -4 1100
carry-out then overflow
-3 1101 +3 0011
1 10001 -1 1111
Simpler addition scheme makes twos complement the most common
choice for integer number systems within digital systems

16. Addition and Subtraction – 2’s
Complement
Why can the carry-out be ignored?
-M + N when N > M:
n n
M* + N = (2 - M) + N = 2 + (N - M)
n
Ignoring carry-out is just like subtracting 2
-M + -N where N + M < = 2n-1
n n
-M + (-N) = M* + N* = (2 - M) + (2 - N)
n n
= 2 - (M + N) + 2
After ignoring the carry, this is just the right two’s complement
representation for -(M + N)!

17. 2’s-Complement Add and
Subtract Operations
(a) 0010 ( + 2) (b) 0100 ( + 4)
+ 0011 ( + 3) + 1010 (- 6)
0101 ( + 5) 1110 (- 2)
(c) 1011 (- 5) (d) 0111 ( + 7)
+ 1110 (- 2) + 1101 ( - 3)
1001 (- 7) 0100 ( + 4)
(e) 1101 (- 3) 1101
- 1001 (- 7) + 0111
0100 ( + 4)
(f) 0010 ( + 2) 0010
- 0100 ( + 4) + 1100
1110 ( - 2)
(g) 0110 ( + 6) 0110
- 0011 ( + 3) + 1101
0011 ( + 3)
(h) 1001 ( - 7) 1001
- 1011 (- 5) + 0101
1110 ( - 2)
(i) 1001 (- 7) 1001
- 0001 ( + 1) + 1111
1000 ( - 8)
(j) 0010 ( + 2) 0010
- 1101 ( - 3) + 0011
0101 ( + 5)
Figure 2.4. 2's-complement Add and Subtract operations.

18. Overflow - Add two positive numbers to get a
negative number or two negative numbers to
get a positive number
-1 +0 -1 +0
-2 1111 0000 +1 -2 1111 0000 +1
1110 0001 1110 0001
-3 +2 -3
1101 1101 +2
0010 0010
-4 -4
1100 0011 +3 1100 0011 +3
-5 1011 -5 1011
0100 +4 0100 +4
1010 1010
-6 0101 -6 0101
1001
+5 +5
0110 1001 0110
-7 1000 0111 +6 -7 1000 +6
0111
-8 +7 -8 +7
5 + 3 = -8 -7 - 2 = +7

19. Overflow Conditions
0111 1000
5 0101 -7 1001
3 0011 -2 1100
-8 1000 7 10111
Overflow Overflow
0000 1111
5 0101 -3 1101
2 0010 -5 1011
7 0111 -8 11000
No overflow No overflow
Overflow when carry-in to the high-order bit does not equal carry out

20. Sign Extension
 Task:
 Given w-bit signed integer x
 Convert it to w+k-bit integer with same value
 Rule:
 Make k copies of sign bit:
 X′= x
w–1 ,…, xw–1 , xw–1 , xw–2 ,…, x0
w
X • • •
k copies of MSB
• • •
X′ • • • • • •
k w

21. Sign Extension Example
short int x = 15213;
int ix = (int) x;
short int y = -15213;
int iy = (int) y;
Decimal Hex Binary
x 15213 3B 6D 00111011 01101101
ix 15213 00 00 C4 92 00000000 00000000 00111011 01101101
y -15213 C4 93 11000100 10010011
iy -15213 FF FF C4 93 11111111 11111111 11000100 10010011

22. Memory Locations,
Addresses, and
Operations

23. Memory Location, Addresses,
and Operation
n bits
first word
 Memory consists
second word
of many millions of
storage cells,
•
each of which can •
•
store 1 bit.
 Data is usually i th word
accessed in n-bit
groups. n is called •
word length. •
•
last word
Figure 2.5. Memory words.

24. Memory Location, Addresses,
and Operation
 32-bit word length example
32 bits
b 31 b 30 b1 b0
•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers
(a) A signed integer
8 bits 8 bits 8 bits 8 bits
ASCII ASCII ASCII ASCII
character character character character
(b) Four characters

25. Memory Location, Addresses,
and Operation
 To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each location
are needed.
 A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
 32-bit memory: 232 = 4G (1G=230)
 1K=210
 1T=240

26. Memory Location, Addresses,
and Operation
 Itis impractical to assign distinct addresses
to individual bit locations in the memory.
 The most practical assignment is to have
successive addresses refer to successive
byte locations in the memory – byte-
addressable memory.
 Byte locations have addresses 0, 1, 2, … If
word length is 32 bits, they successive words
are located at addresses 0, 4, 8,…

27. Big-Endian and Little-Endian
Assignments
Word
address Byte address Byte address
0 0 1 2 3 0 3 2 1 0
4 4 5 6 7 4 7 6 5 4
• •
• •
• •
k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4
(a) Big-endian assignment (b) Little-endian assignment
Figure 2.7. Byte and word addressing.

28. Memory Location, Addresses,
and Operation
 Address ordering of bytes
 Word alignment
 Access numbers, characters, and character
strings

29. Memory Operation
 Load (or Read or Fetch)
 Copy the content. The memory content doesn’t change.
 Address – Load
 Registers can be used
 Store (or Write)
 Overwrite the content in memory
 Address and Data – Store
 Registers can be used

30. Instruction and
Instruction Sequencing

31. “Must-Perform” Operations
 Data transfers between the memory and the
processor registers
 Arithmetic and logic operations on data
 Program sequencing and control
 I/O transfers

32. Register Transfer Notation
 Identifya location by a symbolic name
standing for its hardware binary address
(LOC, R0,…)
 Contents of a location are denoted by placing
square brackets around the name of the
location (R1←[LOC], R3 ←[R1]+[R2])
 Register Transfer Notation (RTN)

33. Assembly Language Notation
 Represent machine instructions and
programs.
 Move LOC, R1 = R1←[LOC]
 Add R1, R2, R3 = R3 ←[R1]+[R2]

34. Basic Instruction Types
 High-levellanguage: C = A + B
 Action: C ← [A] + [B]
 Assembly: Add A, B, C
 Three-address instruction:
Operation Source1, Source2, Destination
 Two-address instruction:
Operation Source, Destination
 Add A, B = B ←[A] + [B]

35. Basic Instruction Types
 Need to add something to the above two-address
instruction to finish:
Move B, C = C ← [B]
 One-address instruction (to fit in one word length)
 Accumulator: Add A
 Load A
 Add B
 Store C
 Zero-address instructions (stack operation)

36. Using Registers
 Registers are faster
 The number of registers is smaller
 Shorter instructions
 Potential speedup
 Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.

37. Using Registers
 Load A, Ri
 Store Ri, A
 Add A, Ri
 Add Ri, Rj
 Add Ri, Rj, Rk
 Move Source, Destination
 Move A, R = Load A, R
i i
 Move Ri, A = Store Ri, A

38. Using Registers
 In the processors where arithmetic operations are
allowed only on operands in register
Move A, Ri
Move B, Rj
Add Ri, Rj
Move Rj, C
 In the processors where one operand may be in the
memory but the other one must be in registers
Move A, Ri
Add B, Ri
Move Ri, C

39. Instruction Execution and
Straight-Line Sequencing
Address Contents
i
Assumptions:
Begin execution here Move A,R0
i +4
3-instruction
program
- One memory operand
Add B,R0
segment per instruction
i +8 Move R0,C
- 32-bit word length
- Memory is byte
addressable
A - Full memory address
can be directly specified
in a single-word instruction
B Data for
the program
Two-phase procedure
C
Figure 2.8. A program for C ← [Α] + [Β].

40. i Move NUM1,R0
i+4 Add NUM2,R0
Branching i+8 Add NUM3,R0
•
•
•
i + 4n - 4 Add NUMn,R0
i + 4n Move R0,SUM
•
•
•
SUM
NUM1
NUM2
•
•
•
NUMn
Figure 2.9. A straight-line program for adding n numbers.

41. Move N,R1
Clear R0
Branching LOOP
Determine address of
"Next" number and add
Program "Next" number to R0
loop
Decrement R1
Branch>0 LOOP
Branch target
Move R0,SUM
Conditional branch
•
•
•
SUM
N n
NUM1
Figure 2.10. Using a loop to add n numbers. NUM2
•
•
•
NUMn

42. Condition Codes
 Condition code flags
 Condition code register / status register
 N (negative)
 Z (zero)
 V (overflow)
 C (carry)
 Different instructions affect different flags

43. Generating Memory Addresses
 How to specify the address of branch target?
 Can we give the memory operand address
directly in a single Add instruction in the
loop?
 Use a register to hold the address of NUM1;
then increment by 4 on each pass through
the loop.

44. Stacks and Queues

45. Stacks
A list of data elements, usually words or
bytes, with the accessing restriction that
elements can be added or removed at one
end of the list only.
 Top / Bottom / Pushdown Stack
 Last-In-First-Out (LIFO)
 Push / Pop

46. Stacks
0
Stack •
pointer •
register •
Current
SP - 28 top element
17
739
Stack
•
•
•
Bottom
BOTTOM 43 element
•
•
•
k
2 - 1
Figure 2.21. A stack of words in the memory.

47. Stacks
 Stack Pointer (SP)
 Push
Subtract #4, SP
Move NEWITEM, (SP)
Move NEWITEM, -(SP)
 Pop
Move (SP), ITEM
Add #4, SP
Move (SP)+, ITEM

48. Stacks
SP 19
- 28 - 28
17 SP 17
739 739
Stack
• •
• •
• •
43 43
NEWITEM 19 ITEM - 28
(a) After push from NEWITEM (b) After pop into ITEM
Figure 2.22. Effect of stack operations on the stack in Figure 2.21.

49. Stacks
 The size of stack in a program is fixed in
memory.
 Need to avoid pushing if the maximum size is
reached
 Need to avoid popping if stack is empty
 Compare instruction
Compare src, dst
[dst] – [src]
Will not change the values of src and dst.

50. Stacks
SAFEPOP Compare #2000,SP Chec to seeif the stac pointer contains
k k
Branc 0
h> EMPTYERR OR an addressvaluegreaterthan 2000. If it
does,the stac is empt . Branc to the
k y h
routine EMPTYERROR for appropriate
action.
Move (SP)+,ITEM Otherwise,pop the top of the stac into
k
memory location ITEM.
(a) Routine for a safe pop operation
SAFEPUSH Compare #1500,SP Chec to seeif the stac pointer
k k
Branc ≤ 0
h FULLERR OR contains an addressvalueequal
to or less than 1500. If it does, the
stac is full. Branc to the routine
k h
FULLERR OR for appropriate action.
Move NEWITEM, – (SP) Otherwise,push the elemen in memory
t
location NEWITEM onto the stac k.
(b) Routine for a safe push operation
Figure 2.23. Checking for empty and full errors in pop and push operations.

51. Queues
 Data are stored in and retrieved from a queue
on a First-In-First-Out (FIFO) basis.
 New data are added at the back (high-
address end) and retrieved from the front
(low-address end).
 How many pointers are needed for stack and
queue, respectively?
 Circular buffer

52. Subroutines

53. Subroutines
 It is often necessary to perform a particular subtask
(subroutine) many times on different data values.
 To save space, only one copy of the instructions
that constitute the subroutine is placed in the
memory.
 Any program that requires the use of the subroutine
simply branches to its starting location (Call).
 After a subroutine has been executed, it is said to
return to the program that called the subroutine, and
the program resumes execution. (Return)

54. Subroutines
 Since the subroutine may be called from different
places in a calling program, provision must be made
for returning to the appropriate location.
 Subroutine Linkage method: use link register to
store the PC.
 Call instruction
 Store the contents of the PC in the link register
 Branch to the target address specified by the instruction
 Return instruction
 Branch to the address contained in the link register

55. Subroutines
Memory Memory
location Calling program location Subroutine SUB
200 Call SUB 1000 first instruction
204 next instruction
Return
1000
PC 204
Link 204
Call Return
Figure 2.24. Subroutine linkage using a link register.

56. Subroutine Nesting and The
Processor Stack
 If a subroutine calls another subroutine, the
contents in the link register will be destroyed.
 If subroutine A calls B, B calls C, after C has
been executed, the PC should return to B,
then A
 LIFO – Stack
 Automatic process by the Call instruction
 Processor stack

57. Parameter Passing
 Exchange of information between a calling
program and a subroutine.
 Several ways:
 Through registers
 Through memory locations
 Through stack

58. Passing Parameters through
Processor Registers
Calling program
Move N,R1 R1 servesas a coun ter.
Move #NUM1,R2 R2 pointsto thelist.
Call LISTADD Call subroutine.
Move R0,SUM Sa result.
ve
.
.
.
Subroutine
LISTADD Clear R0 Initialize sumto 0.
LOOP Add (R2)+,R0 Add entry from list.
Decremen t R1
Branc >0
h LOOP
Return Return to calling program.
Figure 2.25. Program of Figure 2.16 written as a subroutine; parameters passed through registers.

59. Passing Parameters through
Stack
Assumetop of stac is atlevel 1 below.
k
- Passing by reference
Move #NUM1, – (SP) Pushparameters
onto stac
k.
- Passing by value
Move N, – (SP)
Call LISTADD Call subroutine
(top of stac at level 2).
k
Move 4(SP),SUM Sa result.
ve
Add #8,SP Restoretop of stack
(top of stac at level 1).
k
Level 3 → [R2]
.
.
. [R1]
[R0]
LISTADD MoveMultiple R0– R2,– (SP) Sa registers
ve
(top of stac at level 3).
k Level 2 → Return address
Move 16(SP),R1 Initialize coun to n.
ter n
Move 20(SP),R2 Initialize pointer to the list.
Clear R0 Initialize sum to 0. NUM1
LOOP Add (R2)+,R0 Add entry from list. Level 1 →
Decremen t R1
Branch>0 LOOP
Move R0,20(SP) Put result on the stac
k.
MoveMultiple (SP)+,R0 R2
– Restoreregisters. (b) Top of stack at various times
Return Return to calling program.
(a) Calling program and subroutine Figure 2.26. Program of Figure 2.16 written as a subroutine; parameters passed on the stack.

60. The Stack Frame
 Some stack locations constitute a private
work space for a subroutine, created at the
time the subroutine is entered and freed up
when the subroutine returns control to the
calling program. Such space is called a stack
frame.
 Frame pointer (FP)
 Index addressing to access data inside frame
-4(FP), 8(FP), …

61. The Stack Frame
SP saved [R1]
(stack pointer)
saved [R0]
localvar3
localvar2
localvar1 Stack
frame
FP for
(frame pointer) saved [FP]
called
Return address subroutine
param1
param2
param3
param4
Old TOS
(top-of-stack)
Figure 2.27. A subroutine stack frame example.

62. SP and FP
 Move FP, -(SP)
 Move SP, FP
 Subtract #12, SP
 Push R0 and R1
 …
 Pop R0 and R1
 Add #12, SP
 Pop FP
 Return

63. Stack Frames for Nested
Subroutines
Memory
location Instructions Commen
ts
Main program
.
.
.
2000 Move PARAM2, – (SP) Placeparameters stack.
on
2004 Move PARAM1, – (SP)
2008 Call SUB1
2012 Move (SP),RESULT Store result.
2016 Add #8,SP Restorestack level.
2020 next instruction
.
.
.
First subroutine
2100 SUB1 Move FP, – (SP) Sa frame pointer register.
ve
2104 Move SP,FP Load the frame pointer.
2108 MoveMultiple R0– R3,– (SP) Sa registers.
ve
2112 Move 8(FP),R0 Get first parameter.
Move 12(FP),R1 Get secondparameter.
.
.
.
Move PARAM3, – (SP) Placea parameter n stack.
o
2160 Call SUB2
2164 Move (SP)+,R2 Pop SUB2 result into R2.
.
.
.
Move R3,8(FP) Placeansw on stack.
er
MoveMultiple (SP)+,R0– R3 Restoreregisters.
Move (SP)+,FP Restoreframe pointer register.
Return Return to Main program.
Second subroutine
3000 SUB2 Move FP, – (SP) Sa frame pointer register.
ve
Move SP,FP Load the frame pointer.
MoveMultiple R0– R1,– (SP) Sa registers R0 and R1.
ve
Move 8(FP),R0 Get the parameter.
.
.
.
Move R1,8(FP) Place SUB2 result on stack.
MoveMultiple (SP)+,R0– R1 Restoreregisters R0 and R1.
Move (SP)+,FP Restoreframe pointer register.
Return Return to Subroutine 1.
Figure 2.28. Nested subroutines.

64. Stack Frames for Nested
Subroutines
[R1] from SUB1
[R0] from SUB1 Stack
frame
FP [FP] from SUB1 for
second
2164 subroutine
param3
[R3] from Main
[R2] from Main
[R1] from Main
Stack
[R0] from Main frame
for
FP [FP] from Main first
subroutine
2012
param1
param2
Old TOS
Figure 2.29. Stack frames for Figure 2.28.

65. Additional
Instructions

66. Logic Instructions
 AND
 OR
 NOT (what’s the purpose of the following)
Not R0
Add #1, R0
 Determine if the leftmost character of the four ASCII
characters stored in the 32-bit register R0 is Z
(01011010)
And #$FF000000, R0
Compare #$5A000000, R0
Branch=0 YES

67. Logical Shifts
 Logical shift – shifting left (LShiftL) and shifting right
(LShiftR)
C R0 0
before: 0 0 1 1 1 0 . . . 0 1 1
after: 1 1 1 0 . . . 0 1 1 0 0
(a) Logical shift left LShiftL #2,R0
0 R0 C
before: 0 1 1 1 0 . . . 0 1 1 0
after: 0 0 0 1 1 1 0 . . . 0 1
(b) Logical shift irght LShiftR #2,R0

68. Logical Shifts
 Two decimal digits represented in ASCII code are
located at LOC and LOC+1. Pack these two digits in
a single byte location PACKED.
Move #LOC,R0 R0 points to data.
MoveByte (R0)+,R1 Load first byte into R1.
LShiftL #4,R1 Shift left by 4 bit positions.
MoveByte (R0),R2 Load secondbyte into R2.
And #$F,R2 Eliminate high-order bits.
Or R1,R2 ConcatenateheBCD digits.
t
MoveByte R2,PACKED Store the result.
Figure 2.31. A routine that packs two BCD digits.

69. Arithmetic Shifts
R0 C
before: 1 0 0 1 1 . . . 0 1 0 0
after: 1 1 1 0 0 1 1 . . . 0 1
(c) Arithmetic shift rght
i AShiftR #2,R0

70. C R0
before: 0 1 1 1 0 . . . 0 1 1
Rotate
0
after: 1 1 1 0 . . . 0 1 1 0 1
(a) Rotate left without carr
y RotateL #2,R0
C R0
before: 0 0 1 1 1 0 . . . 0 1 1
after: 1 1 1 0 . . . 0 1 1 0 0
(b) Rotate left with carr
y RotateLC #2,R0
R0 C
before: 0 1 1 1 0 . . . 0 1 1 0
after: 1 1 0 1 1 1 0 . . . 0 1
(c) Rotate ight without carr
r y RotateR #2,R0
R0 C
before: 0 1 1 1 0 . . . 0 1 1 0
after: 1 0 0 1 1 1 0 . . . 0 1
(d) Rotate ir with carr
ght y RotateRC #2,R0
Figure 2.32. Rotate instructions.

71. Multiplication and Division
 Not very popular (especially division)
 Multiply R , R
i j
Rj ← [Ri] х [Rj]
 Any problem?
 Divide R , R
i j
Rj ← [Ri] / [Rj]

72. Example Programs

73. Vector Dot Product Program
n −1
Dot Product = ∑ A(i ) × B (i )
i =0
Move #AVEC,R1 R1 points to vector A.
Move #BVEC,R2 R2 points to vector B.
Move N,R3 R3 serv as a coun
es ter.
Clear R0 R0 accum ulates the dot product.
LOOP Move (R1)+,R4 Computethe productof
Multiply (R2)+,R4 nextcomponen ts.
Add R4,R0 Add to previoussum.
Decrement R3 Decrement thecounter.
Branch > 0 LOOP Loop again if not done.
Move R0,DOTPR OD Storedot product in memory.
Figure 2.33. A program for computing the dot product of two vectors.

74. Byte-Sorting Program
 Sort a list of bytes stored in memory into
ascending alphabetic order.
 The list consists of n bytes, not necessarily
distinct, stored from memory location LIST to
LIST+n-1. Each byte contains the ASCII code
for a character from A to Z. The first bit is 0.
 Straight-selection algorithm (compare and
swap)

75. Byte-Sorting Program
for (j = n – 1; j > 0; j = j – 1)
{ for ( k = j – 1; k > = 0; k = k – 1 )
{ if (LIST[k] > LIST[ j])
{ TEMP = LIST[k];
LIST[k] = LIST[ j ];
LIST[ j] = TEMP;
}
}
}
(a) C-language program for sorting
Move #LIST,R0 Load LIST into baseregister R0.
Move N,R1 Initialize outer loop index
Subtract #1,R1 register R1 to j = n – 1.
OUTER Move R1,R2 Initialize inner loop index
Subtract #1,R1 register R2 to k = j – 1.
MoveByte (R0,R1),R3 Load LIST( j ) into R3, which holds
current maximum in sublist.
INNER CompareByte R3,(R0,R2) If LIST( k) ≤ [R3],
Branc ≤ 0
h NEXT do not exhange.
MoveByte (R0,R2),R4 Otherwise,exchange LIST(k)
MoveByte R3,(R0,R2) with LIST(j ) and load
MoveByte R4,(R0,R1) new maximum into R3.
MoveByte R4,R3 RegisterR4 serv esas TEMP.
NEXT Decremen t R2 Decremen index registersR2 and
t
Branc ≥ 0
h INNER R1, which alsoserv e
Decremen t R1 as loop counters, and branc h
Branc 0
h> OUTER back if loopsnot finished.
(b) Assembly language program for sorting

76. Byte-Sorting Program
 The list must have at least two elements
because the check for loop termination is
done at the end of each loop.
 If the machine instruction set allows a move
operation from one memory location directly
to another memory location:
MoveByte (R0, R2), (R0, R1)
MoveByte R3, (R0, R2)
MoveByte (R0, R1), R3

77. Linked List
 Many nonnumeric application programs
require that an ordered list of information
items be represented and stored in memory
in such a way that it is easy to add items to
the list or to delete items from the list at ANY
position while maintaining the desired order
of items.
 Different from Stacks or Queues.

78. Problem Illustration
N n
 Maintain this list of Student ID
LIST
records in consecutive
memory locations in LIST + 4 Test 1
some contiguous Student 1
LIST + 8 Test 2
block of memory in
increasing order of LIST + 12 Test 3
student ID numbers.
LIST + 16 Student ID
 What if a student
withdraws from the Test 1
course so that an Student 2
Test 2
empty record slot is
created? Test 3
 What if another
student registers in •
the course? •
•

79. Linked List
 Each record still occupies a consecutive four-word block in the memory.
 But successive records in the order do not necessarily occupy
consecutive blocks in the memory address space.
 Each record contains an address value in a one-word link field that
specifies the location of the next record in order to enable connecting
the blocks together to form the ordered list.
Link address
Record 1 Record 2 Record k 0
Head Tail
(a) Linking structure
Record 1 Record 2
New record
(b) Inserting a new record between Record 1 and Record 2

80. List in Memory Memory Key Link Data
address field field field
(ID) (Test scores)
1 word 1 word 3 words
First
record 2320 27243 1040 Head
Head pointer
Second
record 1040 28106 1200
Third
record 1200 28370 2880
•
•
•
Second last
record 2720 40632 1280
Last
1280 47871 0 Tail
record
Figure 2.36. A list of student test scores organized as a linked list in memory.

81. Insertion of a New Record
 Suppose that the INSERTION Compare #0, RHEAD
ID number of the
new record is Branch>0 HEAD new record
Move RNEWREC, RHEAD becomes a
28241, and the not empty one-entry list
Return
next available
free record block HEAD Compare (RHEAD), (RNEWREC)
is at address Branch>0 SEARCH
new record
2960. insert new record Move RHEAD, 4(RNEWREC)
becomes
somewhere after Move RNEWREC, RHEAD
 What are the current head
new head
Return
possibilities of the
SEARCH Move RHEAD, RCURRENT
new record’s
Move 4(RCURRENT), RNEXT
position in the list. LOOP
Compare #0, RNEXT
Branch=0 TAIL
ne w record becomes ne tail
w Compare (RNEXT), (RNEWREC)
Branch<0 INSERT
insert new record in Move RNEXT, RCURRENT
an interior position Branch LOOP
INSERT Move RNEXT, 4(RNEWREC)
TAIL Move RNEWREC, 4(RCURRENT)
Return

82. Deletion of a Record
DELETION Compare (RHEAD), RIDNUM
Branch>0 SEARCH
Move 4(RHEAD), RHEAD
not the head record
Return
SEARCH Move RHEAD, RCURRENT
LOOP Move 4(RCURRENT), RNEXT
Compare (RNEXT), RIDNUM
Branch=0 DELETE
Move RNEXT , RCURRENT
Branch LOOP
DELETE Move 4(RNEXT), RTEMP
Move RTEMP , 4(RCURRENT)
Return
Figure 2.38. A subroutine for deleting a record from a linked list. Any problem?

83. Encoding of Machine
Instructions

84. Encoding of Machine
Instructions
 Assembly language program needs to be converted into machine
instructions. (ADD = 0100 in ARM instruction set)
 In the previous section, an assumption was made that all
instructions are one word in length.
 Suppose 32-bit word length, 8-bit OP code (how many
instructions can we have?), 16 registers in total (how many
bits?), 3-bit addressing mode indicator.
 Add R1, R2
8 7 7 10
 Move 24(R0), R5
 LshiftR #2, R0 OP code Source Dest Other info
 Move #$3A, R1
 Branch>0 LOOP (a) One-word instruction

85. Encoding of Machine
Instructions
 What happens if we want to specify a memory
operand using the Absolute addressing mode?
 Move R2, LOC
 14-bit for LOC – insufficient
 Solution – use two words
OP code Source Dest Other info
Memory address/Immediate operand
(b) Two-word instruction

86. Encoding of Machine
Instructions
 Then what if an instruction in which two operands
can be specified using the Absolute addressing
mode?
 Move LOC1, LOC2
 Solution – use two additional words
 This approach results in instructions of variable
length. Complex instructions can be implemented,
closely resembling operations in high-level
programming languages – Complex Instruction Set
Computer (CISC)

87. Encoding of Machine
Instructions
 If we insist that all instructions must fit into a single
32-bit word, it is not possible to provide a 32-bit
address or a 32-bit immediate operand within the
instruction.
 It is still possible to define a highly functional
instruction set, which makes extensive use of the
processor registers.
 Add R1, R2 ----- yes
 Add LOC, R2 ----- no
 Add (R3), R2 ----- yes

88. Encoding of Machine
Instructions
 How to load a 32-bit address into a register that
serves as a pointer to memory locations?
 Solution #1 – direct the assembler to place the
desired address in a word location in a data area
close to the program, so that the Relative
addressing mode can be used to load the address.
 Solution #2 – use logical and shift instructions to
construct the desired 32-bit address by giving it in
parts that are small enough to be specifiable using
the Immediate addressing mode.

89. Encoding of Machine
Instructions
 An instruction must occupy only one word –
Reduced Instruction Set Computer (RISC)
 Other restrictions
OP code Ri Rj Rk Other info
(c) Three-operand instruction