1.  Presented by:-  Presented to:-
 Amrendra prakash(EC-11)  Ravitesh Mishra
 Anil kumar pandit(EC-12) A.P.
 Anjali manjhi (EC-13) BCE Mandideep
 Dayanand kumar(EC-30)
 Madhukar anand (EC-48)
Time taken-30mins March 5, 2013 1

2.  Introduction(PLL)
 Phase detector
 Phase frequency detector(PFD)
 Non ideal effects of PLL
(a)PFD non idealities
(b)Jitter in PLL
 Noise in PLL
 Application of PLL
March 5, 2013 AMRENDRA PRAKASH 2

3. PHASE LOCK LOOPS(PLL)
A PLL is a feedback system that compares the
output phase with the input phase.
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4.  The comparison is performed by a phase comparator or
phase detector(PD)
 Operates on excess phase of x(t) and y(t).
 “Locked” when phase difference between input and
output is constant with time.
 The operation of phase detectors is similar to that of
differential amplifier in which difference between the
two inputs, generating a proportional output.
March 5, 2013 AMRENDRA PRAKASH 4

5. March 5, 2013 ANJALI MANJHI 5

6.  Example of phase detector-
Exclusive OR (XOR) gate
March 5, 2013 ANJALI MANJHI 6

7. For periodic signals, it is possible to merge the two loops by
devising a circuit that can detect both phase and frequency
differences called a PFD.
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8. (1) PFD non idealities
 In practical PFD the delay of the gates creates non-
idealities in the phase input/output characteristic.
 The PFD can no longer resolve very small phase errors, and
a dead zone is created.
 To solve this problem, extra delay is introduced in the
feedback path of reset signal.
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9. •Dead Zone problem-
1)Due to finite gate delay
2) Introduce large jitter or poor phase noise
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10. (2)Jitter in PLL
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11. March 5, 2013 ANIL KUMAR PANDIT 11

12. March 5, 2013 ANIL KUMAR PANDIT 12

13. March 5, 2013 MADHUKAR ANAND 13

14. March 5, 2013 MADHUKAR ANAND 14

15. March 5, 2013 MADHUKAR ANAND 15

16.  Frequency multiplication
March 5, 2013 DAYANAND KUMAR 16

17.  Data recovery(Jitter reduction)
March 5, 2013 DAYANAND KUMAR 17

18.  Skew reduction
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19. March 5, 2013 DAYANAND KUMAR 19