SlideShare a Scribd company logo
1 of 16
ADDRESS
MAPPING
Methods of Address
Mapping :
There are three commonly used methods to
translate main memory addresses to cache
memory addresses.

• Direct-Mapping
• Associative Mapping
• Set-Associative Mapping
BLOCK: Fixed sized packet of information that
moves back and forth between a cache and main
memory.

LINE: Container in a cache that stores a block
as well as other information such as the valid bit
and tag bits.

SET: Collection of one or more lines. Sets in
direct-mapped caches consist of a single line.
Set in fully associative and set associative
caches consists of multiple lines.
Direct-Mapping
• Each cache slot corresponds to an explicit
  set of main memory.
• In our example we have 4096 memory
  blocks and 128 cache slots.
• 128 blocks of main memory save in 1
  block of cache memory.
• It is simplest mapping technique.
• It is easy to implement.
Advantages:
• The tag memory is much smaller than in
  associative mapped cache.
• It is less costly compare to other mapping
  technique.

Disadvantages:
•   It is not flexible.
Associative Mapping
• Any main memory blocks can be
  mapped into each cache slot.
• The 12-tag bits are required to identify a
  memory block when it is in the cache.
• The mapping from main memory blocks to
  cache slots is performed by partitioning an
  address into fields.
• There is no fix block, the memory address
  has only two fields : Tag & Word.
Advantage:
•   Flexibility. Main Memory block can be mapped
    anywhere in Cache Memory.



Disadvantage:
• Slow or expensive.
Set-Associative Mapping
• Combines the simplicity of direct
  mapping with the flexibility of associative
  mapping.
• For this example, two slots make up a
  set. Since there are 214 slots in the
  cache, there are 214/2 =213 sets.
• When an address is mapped to a set, the
  direct mapping scheme is used, and then
  associative mapping is used within a set.

• The format for an address has 13 bits in the
  set field, which identifies the set in which the
  addressed word will be found. Five bits are
  used for the word field and 14-bit tag field.
Advantages:
• In our example the tag memory increases
  only slightly from the direct mapping and only
  two tags need to be searched for each
  memory reference.
• The set-associative cache is widely used in
  today’s microprocessors.
Thank You…

More Related Content

What's hot

Ram and-rom-chips
Ram and-rom-chipsRam and-rom-chips
Ram and-rom-chipsAnuj Modi
 
Bus and memory transfer
Bus and memory transferBus and memory transfer
Bus and memory transferAnil Pokhrel
 
Virtual memory
Virtual memoryVirtual memory
Virtual memoryAnuj Modi
 
Computer architecture memory system
Computer architecture memory systemComputer architecture memory system
Computer architecture memory systemMazin Alwaaly
 
Multiprocessor
MultiprocessorMultiprocessor
MultiprocessorNeel Patel
 
Register organization, stack
Register organization, stackRegister organization, stack
Register organization, stackAsif Iqbal
 
Computer organization memory
Computer organization memoryComputer organization memory
Computer organization memoryDeepak John
 
Memory organization (Computer architecture)
Memory organization (Computer architecture)Memory organization (Computer architecture)
Memory organization (Computer architecture)Sandesh Jonchhe
 
Multithreading
MultithreadingMultithreading
MultithreadingA B Shinde
 
Direct memory access (dma)
Direct memory access (dma)Direct memory access (dma)
Direct memory access (dma)Zubair Khalid
 
Computer Organization and Architecture.
Computer Organization and Architecture.Computer Organization and Architecture.
Computer Organization and Architecture.CS_GDRCST
 

What's hot (20)

Ram and-rom-chips
Ram and-rom-chipsRam and-rom-chips
Ram and-rom-chips
 
Bus and memory transfer
Bus and memory transferBus and memory transfer
Bus and memory transfer
 
Disk scheduling
Disk schedulingDisk scheduling
Disk scheduling
 
Virtual memory
Virtual memoryVirtual memory
Virtual memory
 
Computer architecture memory system
Computer architecture memory systemComputer architecture memory system
Computer architecture memory system
 
Multiprocessor
MultiprocessorMultiprocessor
Multiprocessor
 
Microprogrammed Control Unit
Microprogrammed Control UnitMicroprogrammed Control Unit
Microprogrammed Control Unit
 
Register organization, stack
Register organization, stackRegister organization, stack
Register organization, stack
 
Computer organization memory
Computer organization memoryComputer organization memory
Computer organization memory
 
Memory organization (Computer architecture)
Memory organization (Computer architecture)Memory organization (Computer architecture)
Memory organization (Computer architecture)
 
Paging and segmentation
Paging and segmentationPaging and segmentation
Paging and segmentation
 
Memory Organization
Memory OrganizationMemory Organization
Memory Organization
 
Multithreading
MultithreadingMultithreading
Multithreading
 
Direct memory access (dma)
Direct memory access (dma)Direct memory access (dma)
Direct memory access (dma)
 
Demand paging
Demand pagingDemand paging
Demand paging
 
Multiprocessor system
Multiprocessor system Multiprocessor system
Multiprocessor system
 
mano.ppt
mano.pptmano.ppt
mano.ppt
 
Array Processor
Array ProcessorArray Processor
Array Processor
 
Computer Organization and Architecture.
Computer Organization and Architecture.Computer Organization and Architecture.
Computer Organization and Architecture.
 
Linker and Loader
Linker and Loader Linker and Loader
Linker and Loader
 

Viewers also liked (20)

Memory Mapping Cache
Memory Mapping CacheMemory Mapping Cache
Memory Mapping Cache
 
cache memory
cache memorycache memory
cache memory
 
Memory mapping techniques and low power memory design
Memory mapping techniques and low power memory designMemory mapping techniques and low power memory design
Memory mapping techniques and low power memory design
 
Cache memory presentation
Cache memory presentationCache memory presentation
Cache memory presentation
 
Mapping
MappingMapping
Mapping
 
Memory map
Memory mapMemory map
Memory map
 
Cache memory
Cache memoryCache memory
Cache memory
 
Memory mapping
Memory mappingMemory mapping
Memory mapping
 
Cache memory
Cache memoryCache memory
Cache memory
 
Instruction pipelining
Instruction pipeliningInstruction pipelining
Instruction pipelining
 
Page replacement algorithms
Page replacement algorithmsPage replacement algorithms
Page replacement algorithms
 
Cache mapping
Cache mappingCache mapping
Cache mapping
 
Pipeline and data hazard
Pipeline and data hazardPipeline and data hazard
Pipeline and data hazard
 
Cache memory
Cache memoryCache memory
Cache memory
 
04 Cache Memory
04  Cache  Memory04  Cache  Memory
04 Cache Memory
 
pipelining
pipeliningpipelining
pipelining
 
Introduction to microprocessor
Introduction to microprocessorIntroduction to microprocessor
Introduction to microprocessor
 
The logic behind choosing logic controllers
The logic behind choosing logic controllersThe logic behind choosing logic controllers
The logic behind choosing logic controllers
 
Dhcp
DhcpDhcp
Dhcp
 
Bootstrapping with bootp and dhcp
Bootstrapping with bootp and dhcpBootstrapping with bootp and dhcp
Bootstrapping with bootp and dhcp
 

Similar to Address mapping

How Computer Cache Works
How Computer Cache WorksHow Computer Cache Works
How Computer Cache WorksRishabh Dubey
 
coa-Unit5-ppt1 (1).pptx
coa-Unit5-ppt1 (1).pptxcoa-Unit5-ppt1 (1).pptx
coa-Unit5-ppt1 (1).pptxRuhul Amin
 
Cache Memory for Computer Architecture.ppt
Cache Memory for Computer Architecture.pptCache Memory for Computer Architecture.ppt
Cache Memory for Computer Architecture.pptrularofclash69
 
Set associative mapping
Set associative mappingSet associative mapping
Set associative mappingAshik Khan
 
Computer Organisation and Architecture (COA)
Computer Organisation and Architecture (COA)Computer Organisation and Architecture (COA)
Computer Organisation and Architecture (COA)SwapnitaSrivastava1
 
cache memory introduction, level, function
cache memory introduction, level, functioncache memory introduction, level, function
cache memory introduction, level, functionTeddyIswahyudi1
 
GRP13_CACHE MEMORY ORGANIZATION AND DIFFERENT CACHE MAPPING TECHNIQUES.pptx
GRP13_CACHE MEMORY ORGANIZATION AND DIFFERENT CACHE MAPPING TECHNIQUES.pptxGRP13_CACHE MEMORY ORGANIZATION AND DIFFERENT CACHE MAPPING TECHNIQUES.pptx
GRP13_CACHE MEMORY ORGANIZATION AND DIFFERENT CACHE MAPPING TECHNIQUES.pptxDANCERAMBA
 
Memory Management Strategies - III.pdf
Memory Management Strategies - III.pdfMemory Management Strategies - III.pdf
Memory Management Strategies - III.pdfHarika Pudugosula
 
04_Cache Memory.ppt
04_Cache Memory.ppt04_Cache Memory.ppt
04_Cache Memory.pptShiva340703
 
Computer organization memory hierarchy
Computer organization memory hierarchyComputer organization memory hierarchy
Computer organization memory hierarchyAJAL A J
 

Similar to Address mapping (20)

How Computer Cache Works
How Computer Cache WorksHow Computer Cache Works
How Computer Cache Works
 
Auxiliary, Cache and Virtual memory.pptx
Auxiliary, Cache and Virtual memory.pptxAuxiliary, Cache and Virtual memory.pptx
Auxiliary, Cache and Virtual memory.pptx
 
Cache Memory.pptx
Cache Memory.pptxCache Memory.pptx
Cache Memory.pptx
 
coa-Unit5-ppt1 (1).pptx
coa-Unit5-ppt1 (1).pptxcoa-Unit5-ppt1 (1).pptx
coa-Unit5-ppt1 (1).pptx
 
Cache Memory for Computer Architecture.ppt
Cache Memory for Computer Architecture.pptCache Memory for Computer Architecture.ppt
Cache Memory for Computer Architecture.ppt
 
Cache memory
Cache memoryCache memory
Cache memory
 
COA
COACOA
COA
 
Memory mapping
Memory mappingMemory mapping
Memory mapping
 
Set associative mapping
Set associative mappingSet associative mapping
Set associative mapping
 
cache memory
cache memorycache memory
cache memory
 
Computer Organisation and Architecture (COA)
Computer Organisation and Architecture (COA)Computer Organisation and Architecture (COA)
Computer Organisation and Architecture (COA)
 
cache memory
 cache memory cache memory
cache memory
 
cache memory introduction, level, function
cache memory introduction, level, functioncache memory introduction, level, function
cache memory introduction, level, function
 
GRP13_CACHE MEMORY ORGANIZATION AND DIFFERENT CACHE MAPPING TECHNIQUES.pptx
GRP13_CACHE MEMORY ORGANIZATION AND DIFFERENT CACHE MAPPING TECHNIQUES.pptxGRP13_CACHE MEMORY ORGANIZATION AND DIFFERENT CACHE MAPPING TECHNIQUES.pptx
GRP13_CACHE MEMORY ORGANIZATION AND DIFFERENT CACHE MAPPING TECHNIQUES.pptx
 
Memory Management Strategies - III.pdf
Memory Management Strategies - III.pdfMemory Management Strategies - III.pdf
Memory Management Strategies - III.pdf
 
04 cache memory
04 cache memory04 cache memory
04 cache memory
 
04_Cache Memory.ppt
04_Cache Memory.ppt04_Cache Memory.ppt
04_Cache Memory.ppt
 
Computer organization memory hierarchy
Computer organization memory hierarchyComputer organization memory hierarchy
Computer organization memory hierarchy
 
cache memory.ppt
cache memory.pptcache memory.ppt
cache memory.ppt
 
cache memory.ppt
cache memory.pptcache memory.ppt
cache memory.ppt
 

Recently uploaded

The Fit for Passkeys for Employee and Consumer Sign-ins: FIDO Paris Seminar.pptx
The Fit for Passkeys for Employee and Consumer Sign-ins: FIDO Paris Seminar.pptxThe Fit for Passkeys for Employee and Consumer Sign-ins: FIDO Paris Seminar.pptx
The Fit for Passkeys for Employee and Consumer Sign-ins: FIDO Paris Seminar.pptxLoriGlavin3
 
Why device, WIFI, and ISP insights are crucial to supporting remote Microsoft...
Why device, WIFI, and ISP insights are crucial to supporting remote Microsoft...Why device, WIFI, and ISP insights are crucial to supporting remote Microsoft...
Why device, WIFI, and ISP insights are crucial to supporting remote Microsoft...panagenda
 
A Framework for Development in the AI Age
A Framework for Development in the AI AgeA Framework for Development in the AI Age
A Framework for Development in the AI AgeCprime
 
Rise of the Machines: Known As Drones...
Rise of the Machines: Known As Drones...Rise of the Machines: Known As Drones...
Rise of the Machines: Known As Drones...Rick Flair
 
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptx
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptxPasskey Providers and Enabling Portability: FIDO Paris Seminar.pptx
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptxLoriGlavin3
 
TrustArc Webinar - How to Build Consumer Trust Through Data Privacy
TrustArc Webinar - How to Build Consumer Trust Through Data PrivacyTrustArc Webinar - How to Build Consumer Trust Through Data Privacy
TrustArc Webinar - How to Build Consumer Trust Through Data PrivacyTrustArc
 
The Role of FIDO in a Cyber Secure Netherlands: FIDO Paris Seminar.pptx
The Role of FIDO in a Cyber Secure Netherlands: FIDO Paris Seminar.pptxThe Role of FIDO in a Cyber Secure Netherlands: FIDO Paris Seminar.pptx
The Role of FIDO in a Cyber Secure Netherlands: FIDO Paris Seminar.pptxLoriGlavin3
 
(How to Program) Paul Deitel, Harvey Deitel-Java How to Program, Early Object...
(How to Program) Paul Deitel, Harvey Deitel-Java How to Program, Early Object...(How to Program) Paul Deitel, Harvey Deitel-Java How to Program, Early Object...
(How to Program) Paul Deitel, Harvey Deitel-Java How to Program, Early Object...AliaaTarek5
 
Modern Roaming for Notes and Nomad – Cheaper Faster Better Stronger
Modern Roaming for Notes and Nomad – Cheaper Faster Better StrongerModern Roaming for Notes and Nomad – Cheaper Faster Better Stronger
Modern Roaming for Notes and Nomad – Cheaper Faster Better Strongerpanagenda
 
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptx
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptxMerck Moving Beyond Passwords: FIDO Paris Seminar.pptx
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptxLoriGlavin3
 
What is DBT - The Ultimate Data Build Tool.pdf
What is DBT - The Ultimate Data Build Tool.pdfWhat is DBT - The Ultimate Data Build Tool.pdf
What is DBT - The Ultimate Data Build Tool.pdfMounikaPolabathina
 
Long journey of Ruby standard library at RubyConf AU 2024
Long journey of Ruby standard library at RubyConf AU 2024Long journey of Ruby standard library at RubyConf AU 2024
Long journey of Ruby standard library at RubyConf AU 2024Hiroshi SHIBATA
 
A Deep Dive on Passkeys: FIDO Paris Seminar.pptx
A Deep Dive on Passkeys: FIDO Paris Seminar.pptxA Deep Dive on Passkeys: FIDO Paris Seminar.pptx
A Deep Dive on Passkeys: FIDO Paris Seminar.pptxLoriGlavin3
 
The State of Passkeys with FIDO Alliance.pptx
The State of Passkeys with FIDO Alliance.pptxThe State of Passkeys with FIDO Alliance.pptx
The State of Passkeys with FIDO Alliance.pptxLoriGlavin3
 
Sample pptx for embedding into website for demo
Sample pptx for embedding into website for demoSample pptx for embedding into website for demo
Sample pptx for embedding into website for demoHarshalMandlekar2
 
Emixa Mendix Meetup 11 April 2024 about Mendix Native development
Emixa Mendix Meetup 11 April 2024 about Mendix Native developmentEmixa Mendix Meetup 11 April 2024 about Mendix Native development
Emixa Mendix Meetup 11 April 2024 about Mendix Native developmentPim van der Noll
 
DevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platformsDevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platformsSergiu Bodiu
 
UiPath Community: Communication Mining from Zero to Hero
UiPath Community: Communication Mining from Zero to HeroUiPath Community: Communication Mining from Zero to Hero
UiPath Community: Communication Mining from Zero to HeroUiPathCommunity
 
TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024Lonnie McRorey
 
Scale your database traffic with Read & Write split using MySQL Router
Scale your database traffic with Read & Write split using MySQL RouterScale your database traffic with Read & Write split using MySQL Router
Scale your database traffic with Read & Write split using MySQL RouterMydbops
 

Recently uploaded (20)

The Fit for Passkeys for Employee and Consumer Sign-ins: FIDO Paris Seminar.pptx
The Fit for Passkeys for Employee and Consumer Sign-ins: FIDO Paris Seminar.pptxThe Fit for Passkeys for Employee and Consumer Sign-ins: FIDO Paris Seminar.pptx
The Fit for Passkeys for Employee and Consumer Sign-ins: FIDO Paris Seminar.pptx
 
Why device, WIFI, and ISP insights are crucial to supporting remote Microsoft...
Why device, WIFI, and ISP insights are crucial to supporting remote Microsoft...Why device, WIFI, and ISP insights are crucial to supporting remote Microsoft...
Why device, WIFI, and ISP insights are crucial to supporting remote Microsoft...
 
A Framework for Development in the AI Age
A Framework for Development in the AI AgeA Framework for Development in the AI Age
A Framework for Development in the AI Age
 
Rise of the Machines: Known As Drones...
Rise of the Machines: Known As Drones...Rise of the Machines: Known As Drones...
Rise of the Machines: Known As Drones...
 
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptx
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptxPasskey Providers and Enabling Portability: FIDO Paris Seminar.pptx
Passkey Providers and Enabling Portability: FIDO Paris Seminar.pptx
 
TrustArc Webinar - How to Build Consumer Trust Through Data Privacy
TrustArc Webinar - How to Build Consumer Trust Through Data PrivacyTrustArc Webinar - How to Build Consumer Trust Through Data Privacy
TrustArc Webinar - How to Build Consumer Trust Through Data Privacy
 
The Role of FIDO in a Cyber Secure Netherlands: FIDO Paris Seminar.pptx
The Role of FIDO in a Cyber Secure Netherlands: FIDO Paris Seminar.pptxThe Role of FIDO in a Cyber Secure Netherlands: FIDO Paris Seminar.pptx
The Role of FIDO in a Cyber Secure Netherlands: FIDO Paris Seminar.pptx
 
(How to Program) Paul Deitel, Harvey Deitel-Java How to Program, Early Object...
(How to Program) Paul Deitel, Harvey Deitel-Java How to Program, Early Object...(How to Program) Paul Deitel, Harvey Deitel-Java How to Program, Early Object...
(How to Program) Paul Deitel, Harvey Deitel-Java How to Program, Early Object...
 
Modern Roaming for Notes and Nomad – Cheaper Faster Better Stronger
Modern Roaming for Notes and Nomad – Cheaper Faster Better StrongerModern Roaming for Notes and Nomad – Cheaper Faster Better Stronger
Modern Roaming for Notes and Nomad – Cheaper Faster Better Stronger
 
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptx
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptxMerck Moving Beyond Passwords: FIDO Paris Seminar.pptx
Merck Moving Beyond Passwords: FIDO Paris Seminar.pptx
 
What is DBT - The Ultimate Data Build Tool.pdf
What is DBT - The Ultimate Data Build Tool.pdfWhat is DBT - The Ultimate Data Build Tool.pdf
What is DBT - The Ultimate Data Build Tool.pdf
 
Long journey of Ruby standard library at RubyConf AU 2024
Long journey of Ruby standard library at RubyConf AU 2024Long journey of Ruby standard library at RubyConf AU 2024
Long journey of Ruby standard library at RubyConf AU 2024
 
A Deep Dive on Passkeys: FIDO Paris Seminar.pptx
A Deep Dive on Passkeys: FIDO Paris Seminar.pptxA Deep Dive on Passkeys: FIDO Paris Seminar.pptx
A Deep Dive on Passkeys: FIDO Paris Seminar.pptx
 
The State of Passkeys with FIDO Alliance.pptx
The State of Passkeys with FIDO Alliance.pptxThe State of Passkeys with FIDO Alliance.pptx
The State of Passkeys with FIDO Alliance.pptx
 
Sample pptx for embedding into website for demo
Sample pptx for embedding into website for demoSample pptx for embedding into website for demo
Sample pptx for embedding into website for demo
 
Emixa Mendix Meetup 11 April 2024 about Mendix Native development
Emixa Mendix Meetup 11 April 2024 about Mendix Native developmentEmixa Mendix Meetup 11 April 2024 about Mendix Native development
Emixa Mendix Meetup 11 April 2024 about Mendix Native development
 
DevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platformsDevEX - reference for building teams, processes, and platforms
DevEX - reference for building teams, processes, and platforms
 
UiPath Community: Communication Mining from Zero to Hero
UiPath Community: Communication Mining from Zero to HeroUiPath Community: Communication Mining from Zero to Hero
UiPath Community: Communication Mining from Zero to Hero
 
TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024TeamStation AI System Report LATAM IT Salaries 2024
TeamStation AI System Report LATAM IT Salaries 2024
 
Scale your database traffic with Read & Write split using MySQL Router
Scale your database traffic with Read & Write split using MySQL RouterScale your database traffic with Read & Write split using MySQL Router
Scale your database traffic with Read & Write split using MySQL Router
 

Address mapping

  • 2. Methods of Address Mapping : There are three commonly used methods to translate main memory addresses to cache memory addresses. • Direct-Mapping • Associative Mapping • Set-Associative Mapping
  • 3. BLOCK: Fixed sized packet of information that moves back and forth between a cache and main memory. LINE: Container in a cache that stores a block as well as other information such as the valid bit and tag bits. SET: Collection of one or more lines. Sets in direct-mapped caches consist of a single line. Set in fully associative and set associative caches consists of multiple lines.
  • 4.
  • 6. • Each cache slot corresponds to an explicit set of main memory. • In our example we have 4096 memory blocks and 128 cache slots. • 128 blocks of main memory save in 1 block of cache memory. • It is simplest mapping technique. • It is easy to implement.
  • 7. Advantages: • The tag memory is much smaller than in associative mapped cache. • It is less costly compare to other mapping technique. Disadvantages: • It is not flexible.
  • 8.
  • 9. Associative Mapping • Any main memory blocks can be mapped into each cache slot. • The 12-tag bits are required to identify a memory block when it is in the cache.
  • 10. • The mapping from main memory blocks to cache slots is performed by partitioning an address into fields. • There is no fix block, the memory address has only two fields : Tag & Word.
  • 11. Advantage: • Flexibility. Main Memory block can be mapped anywhere in Cache Memory. Disadvantage: • Slow or expensive.
  • 12.
  • 13. Set-Associative Mapping • Combines the simplicity of direct mapping with the flexibility of associative mapping. • For this example, two slots make up a set. Since there are 214 slots in the cache, there are 214/2 =213 sets.
  • 14. • When an address is mapped to a set, the direct mapping scheme is used, and then associative mapping is used within a set. • The format for an address has 13 bits in the set field, which identifies the set in which the addressed word will be found. Five bits are used for the word field and 14-bit tag field.
  • 15. Advantages: • In our example the tag memory increases only slightly from the direct mapping and only two tags need to be searched for each memory reference. • The set-associative cache is widely used in today’s microprocessors.