1. Digital Logic CircuitsDigital Logic Circuits
By
SATHISHKUMAR G
(sathishsak111@gmail.com)

2. Binary Logic and GatesBinary Logic and Gates
Logic SimulationLogic Simulation
Boolean AlgebraBoolean Algebra
NAND/NOR and XOR gatesNAND/NOR and XOR gates
Decoder fundamentalsDecoder fundamentals
Half Adder, Full Adder, Ripple Carry AdderHalf Adder, Full Adder, Ripple Carry Adder

3. Analog vs DigitalAnalog vs Digital
AnalogAnalog
– ContinuousContinuous
» Time
Every time has a value associated with it, not just some times
» Magnitude
A variable can take on any value within a range
» e.g.
temperature, voltage, current, weight, length, brightness, color

4. Digital SystemsDigital Systems
Digital vs. Analog Waveforms
Analog:
values vary over a broad range
continuously
Digital:
only assumes discrete values
+5
V
–5
Time
+5
V
–5
1 0 1
Time

5. QuantizationQuantization

6. Analog vs DigitalAnalog vs Digital
DigitalDigital
– DiscontinuousDiscontinuous
» Time (discretized)
The variable is only defined at certain times
» Magnitude (quantized)
The variable can only take on values from a finite set
» e.g.
Switch position, digital logic, Dow-Jones Industrial, lottery, batting-average

7. Analog to DigitalAnalog to Digital
A Continuous Signal is Sampled at Some Time and Converted to aA Continuous Signal is Sampled at Some Time and Converted to a
Quantized Representation of its Magnitude at that TimeQuantized Representation of its Magnitude at that Time
– Samples are usually taken at regular intervals and controlled by aSamples are usually taken at regular intervals and controlled by a
clock signalclock signal
– The magnitude of the signal is stored as a sequence of binary valuedThe magnitude of the signal is stored as a sequence of binary valued
(0,1) bits according to some encoding scheme(0,1) bits according to some encoding scheme

8. Digital to AnalogDigital to Analog
A Binary Valued, B = { 0, 1 }, Code Word can be Converted to itsA Binary Valued, B = { 0, 1 }, Code Word can be Converted to its
Analog ValueAnalog Value
Output of D/A Usually Passed Through Analog Low Pass Filter toOutput of D/A Usually Passed Through Analog Low Pass Filter to
Approximate a Continuous SignalApproximate a Continuous Signal
Many Applications Construct a Signal Digitally and then D/AMany Applications Construct a Signal Digitally and then D/A
– e.g., RF Transmitters, Signal Generatorse.g., RF Transmitters, Signal Generators

9. Digital is UbiquitousDigital is Ubiquitous
Electronic Circuits based on Digital Principles are Widely UsedElectronic Circuits based on Digital Principles are Widely Used
– Automotive Engine/Speed ControllersAutomotive Engine/Speed Controllers
– Microwave Oven ControllersMicrowave Oven Controllers
– Heating Duct ControlsHeating Duct Controls
– Digital WatchesDigital Watches
– Cellular PhonesCellular Phones
– Video GamesVideo Games

10. Why Digital?Why Digital?
Increased Noise ImmunityIncreased Noise Immunity
ReliableReliable
InexpensiveInexpensive
ProgrammableProgrammable
Easy to Compute Nonlinear FunctionsEasy to Compute Nonlinear Functions
ReproducibleReproducible
SmallSmall

11. Digital Design ProcessDigital Design Process
Computer Aided Design ToolsComputer Aided Design Tools
– Design entryDesign entry
– SynthesisSynthesis
– Verification and simulationVerification and simulation
– Physical designPhysical design
– FabricationFabrication
– TestingTesting

12. DefinitionDefinition

13. Exclusive-or (Exclusive-or (XOR, EXOR, not-equivalence, ring-ORXOR, EXOR, not-equivalence, ring-OR))
Algebraic symbol:Algebraic symbol:
Gate symbol:Gate symbol:
Representations for combinational logicRepresentations for combinational logic
Truth tablesTruth tables
Graphical (logic gates)Graphical (logic gates)
Algebraic equations (Boolean)Algebraic equations (Boolean)

14. Boolean algebra & logic circuitsBoolean algebra & logic circuits

15. Representations of a Digital DesignRepresentations of a Digital Design
Truth Tables
tabulate all possible input combinations and their associated
output values
Example: half adder
adds two binary digits
to form Sum and Carry
Example: full adder
adds two binary digits and
Carry in to form Sum and
Carry Out
NOTE: 1 plus 1 is 0 with a
carry of 1 in binary
A B
0
0
1
1
0
1
0
1
Sum Carry
0
1
1
0
0
0
0
1
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
Sum
0
1
1
0
1
0
0
1
Cout
0
0
0
1
0
1
1
1

16. Representations of Digital Design:Representations of Digital Design:
Boolean AlgebraBoolean Algebra
NOT X is written as X
X AND Y is written as X & Y, or sometimes X Y
X OR Y is written as X + Y
values: 0, 1
variables: A, B, C, . . ., X, Y, Z
operations: NOT, AND, OR, . . .
A
0
0
1
1
B
0
1
0
1
Sum
0
1
1
0
Carry
0
0
0
1
Sum = A B + A B
Carry = A B
OR'd together product terms
for each truth table
row where the function is 1
if input variable is 0, it appears in
complemented form;
if 1, it appears uncomplemented
Deriving Boolean equations from truth tables:

17. Representations of a DigitalRepresentations of a Digital
Design: Boolean AlgebraDesign: Boolean Algebra
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
Sum
0
1
1
0
1
0
0
1
Cout
0
0
0
1
0
1
1
1
Another example:
Sum = A B Cin + A B Cin + A B Cin + A B Cin
Cout = A B Cin + A B Cin + A B Cin + A B Cin

18. Gate Representations of a Digital DesignGate Representations of a Digital Design
most widely used primitive building block in digital system design
Standard
Logic Gate
Representation
Half Adder Schematic
Netlist: tabulation of gate inputs & outputs
and the nets they are connected to
Net: electrically connected collection of wires
Inverter
AND
OR
Net 1
Net 2
A
B
CARRY
SUM

19. Design methodologyDesign methodology

20. Top-down vs. bottom-up designTop-down vs. bottom-up design

21. Analysis proceduresAnalysis procedures

22. Schematic for 4 Bit ALUSchematic for 4 Bit ALU
AN
D
Gate
OR
Gate
EXO
R
Gate
Inverto
r

23. Simulation of 4 Bit ALUSimulation of 4 Bit ALU
ifif SS=0 then=0 then D=BD=B−−AA
ifif SS=1 then=1 then D=AD=A−−BB
ifif SS=2 then=2 then D=A+BD=A+B
ifif SS=3 then=3 then D=D=−−AAS
B
A
D
4
2
4

24. Elementary Binary Logic FunctionsElementary Binary Logic Functions
Digital circuits represent information using two voltage levels.Digital circuits represent information using two voltage levels.
– binary variablesbinary variables are used to denote these valuesare used to denote these values
– by convention, the values are called “1” and “0” and we often think ofby convention, the values are called “1” and “0” and we often think of
them as meaning “True” and “False”them as meaning “True” and “False”
Functions of binary variables are calledFunctions of binary variables are called logic functionslogic functions..
– AND(AND(AA,,BB) = 1 if) = 1 if AA=1 and=1 and BB=1, else it is zero.=1, else it is zero.
» AND is generally written in the shorthand A⋅B (or A&B or A∧B)
– OR(OR(AA,,BB) = 1 if) = 1 if AA=1 or=1 or BB=1, else it is zero.=1, else it is zero.
» OR is generally written in the shorthand form A+B (or A|B or A∨B)
– NOT(NOT(AA) = 1 if) = 1 if AA=0 else it is zero.=0 else it is zero.
» NOT is generally written in the shorthand form (or ¬A or A′)A
AND, OR and NOT can be used to express all other logic functions.AND, OR and NOT can be used to express all other logic functions.

25. Two Variable Binary Logic FunctionsTwo Variable Binary Logic Functions
Can make similarCan make similar truth tablestruth tables for 3 variable or 4 variable functions,for 3 variable or 4 variable functions,
but gets big (256 & 65,536 columns).but gets big (256 & 65,536 columns).
ZERO
0
0
0
0
A
0
0
1
1
B
0
1
0
1
NOR
1
0
0
0
A′
1
1
0
0
(Β⇒Α)′
0
1
0
0
(Α⇒Β)′
0
0
1
0B′
1
0
1
0
NAND
1
1
1
0
EXOR
0
1
1
0
AND
0
0
0
1
EQUAL
1
0
0
1
Α⇒Β
1
1
0
1
B
0
1
0
1
A
0
0
1
1
Β⇒Α
1
0
1
1
ONE
1
1
1
1
OR
0
1
1
1
Representing functions in terms of AND, OR, NOT.Representing functions in terms of AND, OR, NOT.
– NAND(NAND(AA,,BB) =) = ((AA⋅⋅BB))′′
– EXOR(EXOR(AA,,BB) = () = (AA′⋅′⋅BB)) ++ ((AA⋅⋅BB ′′))

26. Basic Logic GatesBasic Logic Gates
Logic gates “compute” elementary binary functions.Logic gates “compute” elementary binary functions.
– output of an AND gate is “1” when both of its inputs are “1”,output of an AND gate is “1” when both of its inputs are “1”,
otherwise the output is zerootherwise the output is zero
– similarly for OR gate and invertersimilarly for OR gate and inverter
Timing diagram shows how output values change over time asTiming diagram shows how output values change over time as
input values changeinput values change
X
Y X⋅YAND Gate
X X’Inverter
X+Y
X
Y
OR Gate
X’
X⋅Y
X+Y
X
Y
Timing Diagram

27. Multivariable GatesMultivariable Gates
AND function onAND function on nn variables is “1” if and only if ALL itsvariables is “1” if and only if ALL its
arguments are “1”.arguments are “1”.
– nn input AND gate output is “1” if all inputs are “1”input AND gate output is “1” if all inputs are “1”
OR function onOR function on nn variables is “1” if and only if at least one of itsvariables is “1” if and only if at least one of its
arguments is “1”.arguments is “1”.
– nn input OR gate output is “1” if any inputs are “1”input OR gate output is “1” if any inputs are “1”
Can construct “large” gates from 2 input gates.Can construct “large” gates from 2 input gates.
– however, large gates can be less expensive than required number of 2however, large gates can be less expensive than required number of 2
input gatesinput gates
A⋅B⋅C
3 input AND Gate
A+B+C+D+E+F
6 input OR Gate
A
B
C
A
C
B
D
F
E

28. Elements of Boolean AlgebraElements of Boolean Algebra
Boolean algebra defines rules for manipulating symbolic binary logicBoolean algebra defines rules for manipulating symbolic binary logic
expressions.expressions.
– a symbolic binary logic expression consists of binary variables and thea symbolic binary logic expression consists of binary variables and the
operators AND, OR and NOT (e.g.operators AND, OR and NOT (e.g. AA++BB⋅⋅CC′′))
The possible values for any Boolean expression can be tabulated in aThe possible values for any Boolean expression can be tabulated in a
truth tabletruth table..
A B C B⋅C′ A+B⋅C′
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
0
0
1
0
0
0
1
0
1
1
1
1
A
B
C
A+B⋅C′
Can define circuit forCan define circuit for
expression by combiningexpression by combining
gates.gates.

29. Schematic Capture & Logic SimulationSchematic Capture & Logic Simulation
gates
terminals
wires
schematic
entry tools
signal
waveforms
signal
names
advance
simulation

30. Boolean Functions to Logic CircuitsBoolean Functions to Logic Circuits
Any Boolean expression can be converted to a logic circuit made up ofAny Boolean expression can be converted to a logic circuit made up of
AND, OR and NOT gates.AND, OR and NOT gates.
step 1:step 1: add parentheses to expression to fully define order ofadd parentheses to expression to fully define order of
operations -operations - AA+(+(BB⋅(⋅(CC ′′))))
step 2:step 2: create gate for “last” operation in expressioncreate gate for “last” operation in expression
gate’s output is value of expressiongate’s output is value of expression
gate’s inputs are expressions combined by operationgate’s inputs are expressions combined by operation
A
A+B⋅C′
(B⋅(C′))
step 3:step 3: repeat for sub-expressions and continue until donerepeat for sub-expressions and continue until done
Number ofNumber of simplesimple gates needed to implement expression equalsgates needed to implement expression equals
number of operations in expression.number of operations in expression.
– so, simplerso, simpler equivalent expressionequivalent expression yields less expensive circuityields less expensive circuit
– Boolean algebra provides rules for simplifying expressionsBoolean algebra provides rules for simplifying expressions

31. Basic Identities of Boolean AlgebraBasic Identities of Boolean Algebra
1.1. XX ++ 00 == XX
3.3. XX ++ 11 == 11
5.5. XX ++ XX == XX
7.7. XX ++ XX ’’ == 11
9.9. ((XX ’)’’)’ == XX
10.10. XX ++ YY == YY ++ XX
12.12. XX+(+(YY++ZZ )) == ((XX++YY ))++ZZ
14.14. XX((YY++ZZ )) == XX⋅⋅YY ++ XX⋅⋅ZZ
16.16. ((XX ++ YY ))′′ == XX ′⋅′⋅YY ′′
2.2. XX⋅⋅11 == XX
4.4. XX⋅⋅00 == 00
6.6. XX⋅⋅XX == XX
8.8. XX⋅⋅XX ’’ == 00
11.11. XX⋅⋅YY == YY⋅⋅XX
13.13. XX⋅(⋅(YY⋅⋅ZZ )) == ((XX⋅⋅YY ))⋅⋅ZZ
15.15. XX+(+(YY⋅⋅ZZ )) == ((XX++YY ))⋅(⋅(XX++ZZ ))
17.17. ((XX⋅⋅YY)’ =)’ = XX ′+′+YY ′′
commutativecommutative
associativeassociative
distributivedistributive
DeMorgan’sDeMorgan’s
Identities define intrinsic properties of Boolean algebra.Identities define intrinsic properties of Boolean algebra.
Useful in simplifying Boolean expressionsUseful in simplifying Boolean expressions
Note: 15-17 have no counterpart in ordinary algebra.Note: 15-17 have no counterpart in ordinary algebra.
Parallel columns illustrateParallel columns illustrate duality principleduality principle..

32. Verifying Identities Using Truth TablesVerifying Identities Using Truth Tables
Can verify any logical equation with small number of variablesCan verify any logical equation with small number of variables
using truth tables.using truth tables.
Break large expressions into parts, as needed.Break large expressions into parts, as needed.
XX+(+(YY⋅⋅ZZ )) == ((XX++YY ))⋅(⋅(XX++ZZ ))
YY⋅⋅ZZ
00
00
00
11
00
00
00
11
XYZXYZ
000000
001001
010010
011011
100100
101101
110110
111111
XX+(+(YY⋅⋅ZZ ))
00
00
00
11
11
11
11
11
XX++YY
00
00
11
11
11
11
11
11
XX++ZZ
00
11
00
11
11
11
11
11
((XX++YY ))⋅(⋅(XX++ZZ ))
00
00
00
11
11
11
11
11
((XX ++ YY ))′′ == XX ′⋅′⋅YY ′′
XYXY
0000
0101
1010
1111
XX ′⋅′⋅YY ′′
11
00
00
00
((XX ++ YY ))′′
11
00
00
00

33. DeMorgan’s LawDeMorgan’s Law

34. DeMorgan’s Laws forDeMorgan’s Laws for nn VariablesVariables
We can extend DeMorgan’s laws to 3 variables by applying the lawsWe can extend DeMorgan’s laws to 3 variables by applying the laws
for two variables.for two variables.
((XX ++ YY ++ ZZ ))′′== ((XX + (+ (YY ++ ZZ ))))′′ - by associative law- by associative law
== XX ′⋅(′⋅(YY ++ ZZ ))′′ - by DeMorgan’s law- by DeMorgan’s law
== XX ′⋅(′⋅(YY ′⋅′⋅ZZ ′′)) - by DeMorgan’s law- by DeMorgan’s law
== XX ′⋅′⋅YY ′⋅′⋅ZZ ′′ - by associative law- by associative law
((XX⋅⋅YY⋅⋅ZZ))′′ == ((XX⋅(⋅(YY⋅⋅ZZ ))))′′ - by associative law- by associative law
== XX ′′ + (+ (YY⋅⋅ZZ ))′′ -- by DeMorgan’s lawby DeMorgan’s law
== XX ′′ + (+ (YY ′′ ++ ZZ ′′)) - by DeMorgan’s law- by DeMorgan’s law
== XX ′′ ++ YY ′′ ++ ZZ ′′ - by associative law- by associative law
Generalization toGeneralization to nn variables.variables.
– ((XX11 ++ XX22 ++ ⋅ ⋅ ⋅⋅ ⋅ ⋅ ++ XXnn))′′ == XX ′′11⋅⋅XX ′′22 ⋅ ⋅ ⋅⋅ ⋅ ⋅ XX ′′nn
– ((XX11⋅⋅XX22 ⋅ ⋅ ⋅⋅ ⋅ ⋅ XXnn))′′ == XX ′′11 ++ XX ′′22 ++ ⋅ ⋅ ⋅⋅ ⋅ ⋅ ++ XX ′′nn

35. Simplification of Boolean ExpressionsSimplification of Boolean Expressions
F=X ′YZ +X ′YZ ′+XZ
Y
Z
X
Y
Z
X
Y
Z
X
F=X ′Y(Z +Z ′)+XZ
by identity 14
F=X ′Y⋅1+XZ
=X ′Y +XZ by identity 2
by identity 7

36. The Duality PrincipleThe Duality Principle
TheThe dualdual of a Boolean expression is obtained by interchanging allof a Boolean expression is obtained by interchanging all
ANDANDs ands and ORORs, and all 0s and 1s.s, and all 0s and 1s.
– example: the dual ofexample: the dual of AA+(+(BB⋅⋅CC ′′)+0 is)+0 is AA⋅⋅((BB++CC ′′))⋅⋅11
The duality principle states that ifThe duality principle states that if EE11 andand EE22 are Booleanare Boolean
expressions thenexpressions then
EE11== EE22 ⇔⇔ dualdual ((EE11)=)=dualdual ((EE22))
wherewhere dualdual((EE) is the dual of) is the dual of EE. For example,. For example,
AA+(+(BB⋅⋅CC ′′)+0 = ()+0 = (BB ′⋅′⋅CC )+)+DD ⇔⇔ AA⋅⋅((BB++CC ′′))⋅⋅1 = (1 = (BB ′′++CC ))⋅⋅DD
Consequently, the pairs of identities (1,2), (3,4), (5,6), (7,8),Consequently, the pairs of identities (1,2), (3,4), (5,6), (7,8),
(10,11), (12,13), (14,15) and (16,17) all follow from each other(10,11), (12,13), (14,15) and (16,17) all follow from each other
through the duality principle.through the duality principle.

37. The Consensus TheoremThe Consensus Theorem
TheoremTheorem.. XYXY ++ XX ′′ZZ ++YZYZ == XYXY ++ XX ′′ZZ
Proof.Proof. XYXY ++ XX ′′ZZ ++YZYZ == XYXY ++ XX ′′ZZ ++ YZYZ((XX ++ XX ′′) 2,7) 2,7
== XYXY ++ XX ′′ZZ ++ XYZXYZ ++ XX ′′YZYZ 1414
== XYXY ++ XYZXYZ ++ XX ′′ZZ ++ XX ′′YZYZ 1010
== XYXY(1 +(1 + ZZ )) ++ XX ′′ZZ(1 +(1 + YY ) 2,14) 2,14
== XYXY ++ XX ′′ZZ 3,23,2
ExampleExample.. ((AA ++ BB )()(AA′′ ++ CC ) =) = AAAA′′ ++ ACAC ++ AA′′BB ++ BCBC
== ACAC ++ AA′′BB ++ BCBC
== ACAC ++ AA′′BB
DualDual.. ((XX ++ YY ))((XX ′′ ++ ZZ ))((YY ++ ZZ )) == ((XX ++ YY ))((XX ′′ ++ ZZ ))

38. Taking the Complement of a FunctionTaking the Complement of a Function
Method 1Method 1. Apply DeMorgan’s Theorem repeatedly.. Apply DeMorgan’s Theorem repeatedly.
((XX((YY ′′ZZ ′′ ++ YZYZ ))))′′ == XX ′′ + (+ (YY ′′ZZ ′′ ++ YZYZ ))′′
== XX ′′ + (+ (YY ′′ZZ ′′))′′((YZYZ ))′′
== XX ′′ + (+ (YY ++ ZZ )()(YY ′′ ++ ZZ ′′))
Method 2Method 2. Complement literals and take dual. Complement literals and take dual
((XX ((YY ′′ZZ ′′ ++ YZYZ ))))′′== dualdual ((XX ′′((YZYZ ++ YY ′′ZZ ′′))))
== XX ′′ + (+ (YY ++ ZZ )()(YY ′′ ++ ZZ ′′))

39. Sum of Products FormSum of Products Form
TheThe sum of productssum of products is one of twois one of two standard formsstandard forms for Booleanfor Boolean
expressions.expressions.
〈〈sum-of-products-expressionsum-of-products-expression〉〉 == 〈〈termterm〉〉 ++ 〈〈termterm〉〉 ...... ++ 〈〈termterm〉〉
〈〈termterm〉〉 == 〈〈literalliteral〉〉 ⋅⋅ 〈〈literalliteral〉〉 ⋅⋅ ⋅⋅⋅ ⋅⋅⋅⋅ ⋅ 〈〈literalliteral〉〉
Example. XExample. X ′′YY ′′ZZ ++ XX ′′ZZ ++ XYXY ++ XYZXYZ
AA mintermminterm is a term that contains every variable, in eitheris a term that contains every variable, in either
complemented or uncomplemented form.complemented or uncomplemented form.
Example.Example. in expression above,in expression above, XX ′′YY ′′ZZ is minterm, butis minterm, but XX ′′ZZ is notis not
AA sum of minterms expressionsum of minterms expression is a sum of products expression inis a sum of products expression in
which every term is a mintermwhich every term is a minterm
Example.Example. XX ′′YY ′′ZZ ++ XX ′′YZYZ ++ XYZXYZ ′′ ++ XYZXYZ is sum of minterms expression that isis sum of minterms expression that is
equivalent to expression aboveequivalent to expression above

40. Product of Sums FormProduct of Sums Form
TheThe product of sumsproduct of sums is the secondis the second standard formstandard form for Booleanfor Boolean
expressions.expressions.
〈〈product-of-sums-expressionproduct-of-sums-expression〉〉 == 〈〈s-terms-term〉〉 ⋅⋅ 〈〈s-terms-term〉〉 ...... ⋅⋅ 〈〈s-terms-term〉〉
〈〈s-terms-term〉〉 == 〈〈literalliteral〉〉 ++ 〈〈literalliteral〉〉 ++ ⋅⋅⋅⋅⋅⋅ ++ 〈〈literalliteral〉〉
Example.Example. ((XX ′′++YY ′′++ZZ )()(XX ′′++ZZ )()(XX ++YY )()(XX ++YY ++ZZ ))
AA maxtermmaxterm is a sum term that contains every variable, inis a sum term that contains every variable, in
complemented or uncomplemented form.complemented or uncomplemented form.
Example.Example. in exp. above,in exp. above, XX ′′++YY ′′++ZZ is a maxterm, butis a maxterm, but XX ′′++ZZ is notis not
AA product of maxterms expressionproduct of maxterms expression is a product of sums expression inis a product of sums expression in
which every term is a maxtermwhich every term is a maxterm
Example.Example. ((XX ′′++YY ′′++ZZ )()(XX ′′++YY++ZZ )()(XX++Y+ZY+Z ′′)()(XX++YY++ZZ )) is product of maxtermsis product of maxterms
expression that is equivalent to expression aboveexpression that is equivalent to expression above

41. NAND and NOR GatesNAND and NOR Gates
In certain technologies (including CMOS), a NAND (NOR) gate isIn certain technologies (including CMOS), a NAND (NOR) gate is
simpler & faster than an AND (OR) gate.simpler & faster than an AND (OR) gate.
Consequently circuits are often constructed using NANDs and NORsConsequently circuits are often constructed using NANDs and NORs
directly, instead of ANDs and ORs.directly, instead of ANDs and ORs.
Alternative gate representations makes this easier.Alternative gate representations makes this easier.
X
Y (X⋅Y)′NAND Gate (X+Y)′
X
Y
NOR Gate
= =
==

42. Exclusive Or and Odd FunctionExclusive Or and Odd Function
TheThe oddodd function onfunction on nn variables is 1 when an odd number of itsvariables is 1 when an odd number of its
variables are 1.variables are 1.
– odd(odd(X,Y,ZX,Y,Z ) =) = XYXY ′′ZZ ′′++ XX ′′YY ZZ ′′ ++ XX ′′YY ′′ZZ ++ XX YY ZZ == XX ⊕⊕YY ⊕⊕ZZ
– similarly for 4 or more variablessimilarly for 4 or more variables
Parity checkingParity checking circuits use the odd function to provide a simplecircuits use the odd function to provide a simple
integrity check to verify correctness of data.integrity check to verify correctness of data.
– any erroneous single bit change will alter value of odd function, allowingany erroneous single bit change will alter value of odd function, allowing
detection of the changedetection of the change
EXOR gate
Alternative Implementation
A
B
The EXOR function is defined byThe EXOR function is defined by AA⊕⊕BB == ABAB ′′ + A+ A′′B.B.
A
AB ′
+A′B
B

43. Positive and Negative LogicPositive and Negative Logic
InIn positive logicpositive logic systems, a high voltage is associated with a logic 1,systems, a high voltage is associated with a logic 1,
and a low voltage with a logic 0.and a low voltage with a logic 0.
– positive logic is just one of twopositive logic is just one of two conventionsconventions that can be used to associatethat can be used to associate
a logic value with a voltagea logic value with a voltage
– sometimes it is more convenient to use the opposite conventionsometimes it is more convenient to use the opposite convention
In logic diagrams that useIn logic diagrams that use negative logicnegative logic, a, a polarity indicatorpolarity indicator is usedis used
to indicate the correct logical interpretation for a signal.to indicate the correct logical interpretation for a signal.
X
Y X⋅Y X+Y
X
Y
Circuits commonly use a combination of positive and negative logic.Circuits commonly use a combination of positive and negative logic.

44. Analysis exampleAnalysis example

45. Truth tables from logic diagramTruth tables from logic diagram

46. Logic simulationLogic simulation

47. Decoder FundamentalsDecoder Fundamentals
Route data to one specific output line.Route data to one specific output line.
Selection of devices, resourcesSelection of devices, resources
Code conversions.Code conversions.
Arbitrary switching functionsArbitrary switching functions
– implements the AND planeimplements the AND plane
Asserts one-of-many signal; at most one output will beAsserts one-of-many signal; at most one output will be
asserted for any input combinationasserted for any input combination

48. EncodingEncoding
Binary
Decimal Unencoded Encoded
0 0001 00
1 0010 01
2 0100 10
3 1000 11
Note: Finite state machines may be unencoded ("one-hot")
or binary encoded. If the all 0's state is used, then
one less bit is needed and it is called modified
one-hot coding.

49. Why Encode?Why Encode?
A Logarithmic RelationshipA Logarithmic Relationship
N
0 25 50 75 100 125 150
Log2(N)
0
1
2
3
4
5
6
7
8

50. 2:4 Decoder2:4 Decoder
What happens when the inputs goes from 01 to 10?
1 1
1 0
0 1
00
D 0
D 1
A
B
A
B
A
B
A
B
AND 2
AND 2 A
AND 2 A
AND 2 B
Y
Y
Y
Y
E Q 3
E Q 2
E Q 1
E Q 0

51. 2:4 Decoder with Enable2:4 Decoder with Enable
1 1
1 0
0 1
00
1 1
1 0
0 1
00
D 0
D 1
ENABLE
A
B
C
A
B
C
A
B
C
A
B
C
Y
Y
Y
Y
E Q 3
E Q 2
E Q 1
E Q 0
AND 3
AND 3 A
AND 3 A
AND 3 B

52. 2:1 Multiplexer2:1 Multiplexer
A
S
B
A
B
A
B
Y X1
Y X2
A
B
Y Y

53. Design synthesis procedureDesign synthesis procedure

54. Half AdderHalf Adder

55. Full Adder – with EXOR, AND and ORFull Adder – with EXOR, AND and OR

56. Full Adder – with EXOR and NANDFull Adder – with EXOR and NAND
One-bit Full Adder (FA)One-bit Full Adder (FA)
– 3 inputs: A, B, C3 inputs: A, B, C
– 2 outputs: S, Co2 outputs: S, Co
– Truth table:Truth table:
Schematic View:Schematic View:
– cell-based approachcell-based approach
A, B, C S, Co
0, 0, 0 0, 0
0, 0, 1 1, 0
0, 1, 0 1, 0
0, 1, 1 0, 1
1, 0, 0 1, 0
1, 0, 1 0, 1
1, 1, 0 0, 1
1, 1, 1 1, 1
C S
B
A
Co

57. Ripple Carry AdderRipple Carry Adder

58. THANK
YOU
THANK
YOU