MEDI-CAPS UNIVERSITY
Faculty of Engineering
Mr. Sagar Pandya
Information Technology Department
sagar.pandya@medicaps.ac.in
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Computer System Architecture
Mr. Sagar Pandya
Information Technology Department
sagar.pandya@medicaps.ac.in
Course
Code
Course Name Hours Per
Week
Total Hrs. Total
Credits
L T P
IT3CO20 Computer System Architecture 3 1 2 6 5
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Reference Books
� Text Book:
1. Computer System Architecture by Mano, M.M.,, Prentice Hall of India
2. Computer Organization and Architecture, Stallings William, Prentice Hall of
India
3. Computer Architecture and Organization, by Hayes, J.P.,McGraw,Hill
� Reference Books:
1. Computer Organization by V. Carl Hamacher, Safwat G. Zaky and Zvonko G.
Vranesic , McGraw,Hill series
2. Computer Organization and Design, by David Patterson and John Hennessey,”
Elsevier.
3. Computer Systems Design and Architecture (2nd Edition) by Vincent P.
Heuring and Harry F. Jordan etc.
Mr. Sagar Pandya Sagar.pandya@medicaps.ac.in

Unit-1
� Basic architecture and organization of computers,
� Von Neumann Model,
� Registers and storage,
� Register Transfer Language,
� Bus and Memory Transfer, Common Bus System,
� Machine instructions, functional units and execution of a program,
� Instruction cycles,
� Instruction set architectures,
� Instruction formats.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
� Computer technology has made incredible improvement in the past
half century.
� In the early part of computer evolution, there were no stored-
program computer, the computational power was less and on the top
of it the size of the computer was a very huge one.
� Today, a personal computer has more computational power, more
main memory, more disk storage, smaller in size and it is available in
affordable cost.
� This rapid rate of improvement has come both from advances in the
technology used to build computers and from innovation in computer
design.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
� The task that the computer designer handles is a complex one:
Determine what attributes are important for a new machine, then
design a machine to maximize performance while staying within cost
constraints.
� This task has many aspects, including instruction set design,
functional organization, logic design, and implementation.
� While looking for the task for computer design, both the terms
computer organization and computer architecture come into picture.
� It is difficult to give precise definition for the terms Computer
Organization and Computer Architecture.
� But while describing computer system, we come across these terms,
and in literature, computer scientists try to make a distinction
between these two terms.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
� Computer architecture refers to those parameters of a computer
system that are visible to a programmer or those parameters that
have a direct impact on the logical execution of a program.
� Examples of architectural attributes include the instruction set, the
number of bits used to represent different data types, I/O
mechanisms, and techniques for addressing memory.
� Computer organization refers to the operational units and their
interconnections that realize the architectural specifications.
� Examples of organizational attributes include those hardware details
transparent to the programmer, such as control signals, interfaces
between the computer and peripherals, and the memory technology
used.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
S.No Computer Architecture Computer Organization
1 Computer Architecture is
concerned with the way
hardware components are
connected together to form a
computer system.
Computer Organization is
concerned with the structure and
behaviour of a computer system
as seen by the user.
2 It acts as the interface between
hardware and software.
It deals with the components of a
connection in a system.
3 Computer Architecture helps
us to understand the
functionalities of a system.
Computer Organization tells us
how exactly all the units in the
system are arranged and
interconnected.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
S.No Computer Architecture Computer Organization
4 A programmer can view
architecture in terms of
instructions, addressing modes
and registers.
Whereas Organization
expresses the realization of
architecture.
5 Computer Architecture deals
with high-level design issues.
Computer Organization deals
with low-level design issues.
6 Architecture involves Logic
(Instruction sets, Addressing
modes, Data types, Cache
optimization)
Organization involves Physical
Components (Circuit design,
Adders, Signals, Peripherals)
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
� If you had watched a magic show then you would have seen that the
magician puts some colored bits of paper inside his hat, mumbles
some magic words and then pulls out a rabbit! And you begin to
wonder because what went in did not come out.
� The computer can perform some magic too.
� For example, it can add large numbers and make other complex
calculations and give you the result in just a few (seconds. Thus
many actions of computer appear as magic.
� Just as a human being can be seen as a combination of body and
mind, the same toes for a computer.
� The computer is a two part system consisting of a body and mind.
The body of the computer is the hardware such as CPU, VDU, etc.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
� These are the mechanical and electronic parts which can be seen and
touched.
� The mind of the computer is the software. It consists of commands
and instructions.
� Therefore a computer is a collection of electronic parts (body) with a
set of instructions controlling it (mind).
� Almost all the systems and the machines that we find around us work
in the same ray. They accept some Input.
� These inputs are processed in a specific manner to produce some
Output.
� For example, we take oranges, put them in the juicer, switch I on and
finally we get orange juice.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� I-P-O Cycle:
� The I-P-O (Input-Process-Output) cycle can be illustrated with the
help of an example of adding numbers.
� Suppose you are asked to add two numbers 40 and 50. When you are
told to add these two numbers you perform this addition by the
factoring processes:
� First, you hear the two numbers.
� Then you store the numbers in your memory.
� Your brain adds the two numbers.
� Then the result (40 + 50 = 90) is stored in your memory.
� You either speak out the result loudly or write it down, depending on
what is required.

INTRODUCTION
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� This Input-Process-Output (I-P-O) cycle is represented in the
following figure:
� Now let's evaluate the entire procedure in the form of Input-Process-
Output cycle. The numbers that you have to add are called input. The
method of addition is called process and the final result is called
output. Here, the inputs are 40 and 50.
� The output is 90. Your ear is the input device, the brain is the
processing unit and mouth is the output device.

INTRODUCTION – Model of Computer
� The model of a computer can be described by four basic units in high
level abstraction. These basic units are:
� Central Processor Unit
� Input Unit
� Output Unit
� Memory Unit
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
A. Central Processor Unit [CPU] :
� Central processor unit consists of two basic blocks :
� The program control unit has a set of registers and control circuit to
generate control signals.
� The execution unit or data processing unit contains a set of registers
for storing data and an Arithmetic and Logic Unit (ALU) for
execution of arithmetic and logical operations.
� In addition, CPU may have some additional registers for temporary
storage of data.
B. Input Unit :
� With the help of input unit data from outside can be supplied to the
computer.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
� Program or data is read into main storage from input device or
secondary storage under the control of CPU input instruction.
� Example of input devices: Keyboard, Mouse, Hard disk, Floppy disk,
CD-ROM drive etc.
C. Output Unit :
� With the help of output unit computer results can be provided to the
user or it can be stored in storage device permanently for future use.
� Output data from main storage go to output device under the control
of CPU output instructions.
� Example of output devices: Printer, Monitor, Plotter, Hard Disk,
Floppy Disk etc.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
D. Memory Unit :
� Memory unit is used to store the data and program. CPU can work
with the information stored in memory unit.
� This memory unit is termed as primary memory or main memory
module. These are basically semi conductor memories.
� There ate two types of semiconductor memories -
� Volatile Memory : RAM (Random Access Memory).
� Non-Volatile Memory : ROM (Read only Memory), PROM
(Programmable ROM)
� EPROM (Erasable PROM), EEPROM (Electrically Erasable
PROM).
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

INTRODUCTION
� Secondary Memory :
� There is another kind of storage device, apart from primary or main
memory, which is known as secondary memory.
� Secondary memories are non volatile memory and it is used for
permanent storage of data and program.
� Example of secondary memories:
� Magnetic Devices :- Hard Disk, Floppy Disk, Magenetic Tape.
� Optical Device :- CD-ROM
� Semiconductor Memory :- Thumb drive (or pen drive)
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

General System Architecture
� In Computer Architecture, the General System Architecture is
divided into two major classification units.
1. Store Program Control Concept
2. Flynn's Classification of Computers
1. Store Program Control Concept
� The term Stored Program Control Concept refers to the storage of
instructions in computer memory to enable it to perform a variety of
tasks in sequence or intermittently.
� The idea was introduced in the late 1940s by John von Neumann
who proposed that a program be electronically stored in the binary-
number format in a memory device so that instructions could be
modified by the computer as determined by intermediate
computational results.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

General System Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� ENIAC (Electronic Numerical Integrator and Computer) was the first
computing system designed in the early 1940s. It was based on
Stored Program Concept in which machine use memory for
processing data.

General System Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Stored Program Concept can be further classified in three basic
ways:
� Von-Neumann Model
� General Purpose System
� Parallel Processing
� 1. Von-Neumann Architecture:
� Von Neumann architecture was first published by John von
Neumann in 1945.
� His computer architecture design consists of a Control Unit,
Arithmetic and Logic Unit (ALU), Memory Unit, Registers and
Inputs/Outputs.

Von-Neumann Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Von-Neumann Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The modern computers are based on a stored-program concept
introduced by John Von Neumann.
� In this stored-program concept, programs and data are stored in a
separate storage unit called memories and are treated the same.
� This novel idea meant that a computer built with this architecture
would be much easier to reprogram.
� It is also known as IAS computer and is having three basic units:
� The Central Processing Unit (CPU)
� The Main Memory Unit
� The Input/Output Device

Von-Neumann Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Von-Neumann Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Von Neumann architecture is based on the stored-program computer
concept, where instruction data and program data are stored in the
same memory.
� This design is still used in most computers produced today.
� Central Processing Unit (CPU)
� The Central Processing Unit (CPU) is the electronic circuit
responsible for executing the instructions of a computer program.
� It is sometimes referred to as the microprocessor or processor.
� The CPU contains the ALU, CU and a variety of registers.
� Registers: Registers are high speed storage areas In the CPU. All
data must be stored in register before it can be processed.

Von-Neumann Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Main Memory Unit (Registers) –
� Accumulator: Stores the results of calculations made by ALU.
� Program Counter (PC): Keeps track of the memory location of the
next instructions to be dealt with. The PC then passes this next
address to Memory Address Register (MAR).
� Memory Address Register (MAR): It stores the memory locations
of instructions that need to be fetched from memory or stored into
memory.
� Memory Data Register (MDR): It stores instructions fetched from
memory or any data that is to be transferred to, and stored in,
memory.

Von-Neumann Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Current Instruction Register (CIR): It stores the most recently
fetched instructions while it is waiting to be coded and executed.
� Instruction Buffer Register (IBR): The instruction that is not to be
executed immediately is placed in the instruction buffer register IBR.
� Input/Output Devices – Program or data is read into main memory
from the input device or secondary storage under the control of CPU
input instruction.
� Output devices are used to output the information from a computer.
� If some results are evaluated by computer and it is stored in the
computer, then with the help of output devices, we can present it to
the user.

Von-Neumann Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Arithmetic and Logic Unit (ALU)
� The ALU allows arithmetic (add, subtract etc) and logic (AND, OR,
NOT etc) operations to be carried out.
� Control Unit (CU)
� The control unit controls the operation of the computer’s ALU,
memory and input/output devices, telling them how to respond to the
program instructions it has just read and interpreted from the
memory unit.
� The control unit also provides the timing and control signals required
by other computer components.
� Buses
� A standard CPU system bus is comprised of a control bus, data bus
and address

Von-Neumann Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Buses are the means by which data is transmitted from one part of a
computer to another, connecting all major internal components to the
CPU and memory.
Address Bus
Carries the addresses of data (but not the data) between
the processor and memory
Data Bus
Carries data between the processor, the memory unit
and the input/output devices
Control Bus
Carries control signals/commands from the CPU (and
status signals from other devices) in order to control
and coordinate all the activities within the computer

Von-Neumann Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Memory Unit
� The memory unit consists of RAM, sometimes referred to as primary
or main memory.
� Unlike a hard drive (secondary memory), this memory is fast and
also directly accessible by the CPU.
� RAM is split into partitions. Each partition consists of an address
and its contents (both in binary form).
� The address will uniquely identify every location in the memory.
� Loading data from permanent memory (hard drive), into the faster
and directly accessible temporary memory (RAM), allows the CPU
to operate much quicker.

Flynn’s Classification of Computer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Parallel computing is a computing where the jobs are broken into
discrete parts that can be executed concurrently.
� Each part is further broken down to a series of instructions.
Instructions from each part execute simultaneously on different
CPUs.
� Parallel systems deal with the simultaneous use of multiple computer
resources that can include a single computer with multiple
processors, a number of computers connected by a network to form a
parallel processing cluster or a combination of both.
� Parallel systems are more difficult to program than computers with a
single processor because the architecture of parallel computers varies
accordingly and the processes of multiple CPUs must be coordinated
and synchronized.

Flynn’s Classification of Computer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� M.J. Flynn proposed a classification for the organization of a
computer system by the number of instructions and data items that
are manipulated simultaneously.
� The sequence of instructions read from memory constitutes an
instruction stream.
� The operations performed on the data in the processor constitute a
data stream.
� The term 'Stream' refers to the flow of instructions or data.
� Parallel processing may occur in the instruction stream, in the data
stream, or both.
� Flynn's classification divides computers into four major groups that
are:
� 1. Single instruction stream, single data stream (SISD)

Flynn’s Classification of Computer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Single instruction stream, multiple data stream (SIMD)
� Multiple instruction stream, single data stream (MISD)
� Multiple instruction stream, multiple data stream (MIMD)

Flynn’s Classification of Computer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Single-instruction, single-data (SISD) systems –
� An SISD computing system is a uniprocessor machine which is
capable of executing a single instruction, operating on a single data
stream.
� In SISD, machine instructions are processed in a sequential manner
and computers adopting this model are popularly called sequential
computers.
� Most conventional computers have SISD architecture.
� All the instructions and data to be processed have to be stored in
primary memory.

Flynn’s Classification of Computer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The speed of the processing element in the SISD model is
limited(dependent) by the rate at which the computer can transfer
information internally. Dominant representative SISD systems are
IBM PC, workstations.

Flynn’s Classification of Computer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Single-instruction, multiple-data (SIMD) systems –
� An SIMD system is a multiprocessor machine capable of executing
the same instruction on all the CPUs but operating on different data
streams.
� Machines based on an SIMD model are well suited to scientific
computing since they involve lots of vector and matrix operations.
� So that the information can be passed to all the processing elements
(PEs) organized data elements of vectors can be divided into multiple
sets(N-sets for N PE systems) and each PE can process one data set.
� Dominant representative SIMD systems is Cray’s vector processing
machine.

Flynn’s Classification of Computer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Single-instruction, multiple-data (SIMD) systems –

Flynn’s Classification of Computer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Multiple-instruction, single-data (MISD) systems –
� An MISD computing system is a multiprocessor machine capable of
executing different instructions on different PEs but all of them
operating on the same dataset .
� Example Z = sin(x)+cos(x)+tan(x). The system performs different
operations on the same data set.
� Machines built using the MISD model are not useful in most of the
application, a few machines are built, but none of them are available
commercially.

Flynn’s Classification of Computer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Multiple-instruction, multiple-data (MIMD) systems –
� An MIMD system is a multiprocessor machine which is capable of
executing multiple instructions on multiple data sets.
� Each PE in the MIMD model has separate instruction and data
streams; therefore machines built using this model are capable to any
kind of application.
� Unlike SIMD and MISD machines, PEs in MIMD machines work
asynchronously.
� MIMD machines are broadly categorized into shared-memory
MIMD and distributed-memory MIMD based on the way PEs are
coupled to the main memory.

Flynn’s Classification of Computer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� In the shared memory MIMD model (tightly coupled multiprocessor
systems), all the PEs are connected to a single global memory and
they all have access to it. In Distributed memory MIMD machines
(loosely coupled multiprocessor systems) all PEs have a local
memory.

EVOLUTION OF INTEL X86
ARCHITECTURE:
� We have Two computer families: the Intel x86 and the ARM
architecture.
� The current x86 offerings represent the results of decades of design
effort on complex instruction set computers (CISCs).
� The x86 incorporates the sophisticated design principles once found
only on mainframes and supercomputers and serves as an excellent
example of CISC design.
� An alternative approach to processor design in the reduced
instruction set computer (RISC).
� The ARM architecture is used in a wide variety of embedded
systems and is one of the most powerful and best-designed RISC-
based systems on the market.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

EVOLUTION OF INTEL X86
ARCHITECTURE:
� In terms of market share, Intel has ranked as the number one maker
of microprocessors for non-embedded systems for decades, a
position it seems unlikely to yield.
� Interestingly, as microprocessors have grown faster and much more
complex, Intel has actually picked up the pace.
� It is worthwhile to list some of the highlights of the evolution of the
Intel product line:
� 8080:
� The world’s first general-purpose microprocessor.
� This was an 8-bit machine, with an 8-bit data path to memory.
� The 8080 was used in the first personal computer, the Altair.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

EVOLUTION OF INTEL X86
ARCHITECTURE:
� 8086:
� A far more powerful, 16-bit machine. In addition to a wider data path
and larger registers, the 8086 sported an instruction cache, or queue,
that prefetches a few instructions before they are executed.
� A variant of this processor, the 8088, was used in IBM’s first
personal computer, securing the success of Intel.
� The 8086 is the first appearance of the x86 architecture.
� 80286:
� This extension of the 8086 enabled addressing a 16-MByte memory
instead of just 1 MByte. •
� 80386:
� Intel’s first 32-bit machine, and a major overhaul of the product.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

EVOLUTION OF INTEL X86
ARCHITECTURE:
� With a 32-bit architecture, the 80386 rivaled the complexity and
power of minicomputers and mainframes introduced just a few years
earlier.
� This was the first Intel processor to support multitasking, meaning it
could run multiple programs at the same time.
� 80486: The 80486 introduced the use of much more sophisticated
and powerful cache technology and sophisticated instruction
pipelining. T
� he 80486 also offered a built-in math coprocessor, offloading
complex math operations from the main CPU.
� Pentium: With the Pentium, Intel introduced the use of superscalar
techniques, which allow multiple instructions to execute in parallel.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

EVOLUTION OF INTEL X86
ARCHITECTURE:
� Pentium Pro: The Pentium Pro continued the move into superscalar
organization begun with the Pentium, with aggressive use of register
renaming, branch prediction, data flow analysis, and speculative
execution.
� Pentium II: The Pentium II incorporated Intel MMX technology,
which is designed specifically to process video, audio, and graphics
data efficiently.
� Pentium III: The Pentium III incorporates additional floating-point
instructions to support 3D graphics software.
� Pentium 4: The Pentium 4 includes additional floating-point and
other enhancements for multimedia.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

EVOLUTION OF INTEL X86
ARCHITECTURE:
� Core: This is the first Intel x86 microprocessor with a dual core,
referring to the implementation of two processors on a single chip.
� Core 2: The Core 2 extends the architecture to 64 bits. The Core 2
Quad provides four processors on a single chip.
� The x86 provides an excellent illustration of the advances in
computer hardware over the past 30 years.
� The 1978, 8086 was introduced with a clock speed of 5 MHz and had
29,000 transistors.
� A quad-core Intel Core 2 introduced in 2008 operates at 3 GHz, a
speedup of a factor of 600, and has 820 million transistors, about
28,000 times as many as the 8086.
� Yet the Core 2 is in only a slightly larger package than the 8086 and
has a comparable cost.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� In Computer Architecture, the Registers are very fast computer
memory which are used to execute programs and operations
efficiently.
� Registers are a type of computer memory used to quickly accept,
store, and transfer data and instructions that are being used
immediately by the CPU.
� The registers used by the CPU are often termed as Processor
registers.
� A processor register may hold an instruction, a storage address, or
any data (such as bit sequence or individual characters).
� The computer needs processor registers for manipulating data and a
register for holding a memory address.

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The register holding the memory location is used to calculate the
address of the next instruction after the execution of the current
instruction is completed.
� The most important thing about Registers is that Registers generally
hold data temporarily, during execution of a program And Registers
are normally measured by the number of bits they can hold.
� As an example: An 8-bit register means, it can store 8 bit of data,
32-bit register means it can store 32 bit of data.
� Data and instructions must be put into the system. So we need
registers for this.
� Following is the list of some of the most common registers used in a
basic computer:

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
Register
Symbol
Register Name
Number
of Bits
Description
AC Accumulator 16 Processor Register
DR Data Register 16 Hold memory data
TR Temporary Register 16 Holds temporary Data
IR Instruction Register 16 Holds Instruction Code
AR Address Register 12 Holds memory address
PC Program Counter 12 Holds address of next instruction
INPR Input Register 8 Holds Input data
OUTR Output Register 8 Holds Output data

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The Memory unit has a capacity of 4096 words, and each word
contains 16 bits.
� The Data Register (DR) contains 16 bits which hold the operand read
from the memory location.
� The Memory Address Register (MAR) contains 12 bits which hold the
address for the memory location.
� The Program Counter (PC) also contains 12 bits which hold the
address of the next instruction to be read from memory after the
current instruction is executed.
� The Accumulator (AC) register is a general purpose processing
register.
� The instruction read from memory is placed in the Instruction register
(IR).

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The Temporary Register (TR) is used for holding the temporary data
during the processing.
� The Input Registers (IR) holds the input characters given by the
user.
� The Output Registers (OR) holds the output after processing the
input data.
� Now, thus, according to Basic computer, whose CPU is of 16 bit
and memory is of 212*16=4096 words, of 16 bits each, and
according to definition of each type of register we discussed, the no.
of bits allocated to each register is depicted in Figure.
� Here we assume that EBCDIC code is followed in computer.

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� PC Register
� PC stands for “Program Counter” register, and it is also known as
Instruction Pointer (IP) in the Microprocessors, but sometimes few
people is known as named with “Instruction Address Register”.
� Program Counter register’s function is to hold all records in sequence
of entire execution of programs.
� PC has the memory address of further instruction that is fetched in
next step.
� PC registers to keep track the address of next instruction which to be
fetched from the primary memory, if recently instruction is
completely executed.
� It helps to count all numbers of entire instructions.

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� AC Register
� AC register is also called of the “Accumulator Register“, because this
register holds the integer values which are needed by the ALU
(Arithmetically Logical Unit) while executing of any specific instruction.
� Accumulator Register is a general purpose Register. Main function of
Accumulator Register is to store the output which is generated by your
system.
� When CPU (Center Processing Unit) will execute some instruction then it
will produce the result, now AC register is needed to store those
produced data.
� And the number of bits that accumulator register contain is equal to the
number of bits per word. That is, if word is of n bits, the AC is also of n
bits.

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� MAR Register
� MAR stand for “Memory Address Register”, and its main objective
is to store all memory addresses of entire data and instructions.
� MAR helps to make the communication with using of MDR
(Memory Data Register) in between the CPU and Main Memory.
� For example – If, CPU (Center Processing Unit) needs to hold few
data in to Primary Memory otherwise to fetch some data from
memory side, then it places those addresses which are needed into
main memory in the MAR (Memory Address Register).
� Index Register
� Index register helps to update operand while running of the programs
in the computer’s CPU.

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� MDR Register
� MDR stands for “Memory Data Register“, and this register is needed
after completing the execution in PC register.
� CPU fetches some mandatory instructions and data from main
memory side then its temporary copy is saved into this data register
before decoding this data. So, MDR register works as a middle
buffer.
� IR Register
� IR stands for “Instruction Register“, and this register is used to store
those data which are needed in currently execution period.
� So, the no. of bits(size) of Instruction Register is equal to the no. of
bits of instruction, and the size of instruction is n bit for n-bit
CPU.

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Temporary Register(TR):
� Temporary Register(TR) is used for holding data during the
processing And since Temporary Register hold data, so, the no. of
bits it contain is equal to no. of bits of word(data word).
� Data Register(DR):
� The Data Register hold the operand from memory. Means when an
operand is found, using either direct or indirect addressing, it is
placed in Data Register(DR).
� The processor then used in this value as data for its operation.
� Its size is equal to the size of word in memory.

Registers and Storage
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Input Register(INPR):
� Input Register(INPR) hold(or receives) data from an input device
And the size of input register is depend on the alphanumeric code
that followed in computer, that is, if ASCII is followed, then the
size of INPR is 7 bits and if EBCDIC is followed, then the size of
INPR is 8 bits.
� Output Register(OUTR):
� Output Register(OUTR) hold data that need to be sent to an output
device. Its size is also depend on the alphanumeric code that
followed in computer.

Registers Transfer Language
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The symbolic notation used to describe the microoperation transfers
among registers is called a register transfer language.
� Digital modules are best defined by the registers they contain and the
operations executed that are performed on the data stored in them.
� The operations executed on data stored in registers are called
microoperations.
� A microoperations is an elementary operation performed on the
information stored in one or more registers.
� The result of the operation may replace the previous binary of a
register or may be transferred to another register.
� Examples of microoperations are in shift, count, clear and load.

Registers Transfer Language
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The term "register transfer" implies the availability of hardware logic
circuits that can perform a stated microoperation and transfer the
result of the operation to the same or another register.
� The word "language" is borrowed from programmers, who apply this
term to programming languages.
� A programming language is a procedure for writing symbols to
specify a given computational process.
� Similarly, a natural language such as English is a system for writing
symbols and combining them into words and sentences for the
purpose of communication between people.
� A register transfer language is a system for expressing in symbolic
form the microoperation sequences among the registers of a digital
module.

Registers Transfer Language
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� It is a convenient tool for describing the internal organization of
digital computers in concise and precise manner.
� It can also be used to facilitate the design process of digital systems.
� Computer registers are designated by capital letters (sometimes
followed by numerals) to denote the function of the register.
� For example, the register that holds an address for the memory unit is
usually called a memory address register and is designated by the
name MAR.
� Other designations for registers are PC (for program counter), IR (for
instruction register, and R 1 (for processor register).
� The individual flip-flops in an n-bit register are numbered in
sequence from 0 through n - 1, starting from 0 in the rightmost
position and increasing the numbers toward the left.

Registers Transfer Language
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Figure 4-1 shows the representation of registers in block diagram form.
� The most common way to represent a register is by a rectangular box
with the name of the register inside, as in Fig. 4-1(a).
� The individual bits can be distinguished as in (b).
� The numbering of bits in a 16-bit register can be marked on top of the
box as shown in (c).
� A 16-bit register is partitioned into two parts in (d).
� Bits 0 through 7 are assigned the symbol L (for low byte) and bits 8
through 15 are assigned the symbol H (for high byte).
� The name of the 16-bit register is PC . The symbol PC(0-7) or PC(L)
refers to the low-order byte and PC(S-15) or PC( H) to the high-order
byte.

Registers Transfer Language
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Registers Transfer Language
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Information transfer from one register to another is designated in
symbolic form by means of a replacement operator.
� The statement R2 🡨 R1 denotes a transfer of the content of register
R1 into register R2.
� It designates a replacement of the content of R2 by the content of Rl.
� By definition, the content of the source register R1 does not change
after the transfer.
� Normally, we want the transfer to occur only under a predetermined
control condition.
� This can be shown by means of an if-then statement.
� If (P = 1) then (R2 <-- R1)
� Where P is a control signal generated in the control section.

Registers Transfer Language
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� It is sometimes convenient to separate the control variables from the
register transfer operation by specifying a control function.
� A control function is a Boolean variable that is equal to 1 or 0.
� The control function is included in the statement as follows:
� P: R2 <-- R1
� The control condition is terminated with a colon.
� It symbolizes the requirement that the transfer operation be executed
by the hardware only if P = 1.
� Registers are denoted by capital letters, and numerals may follow the
letters.
� Parentheses are used to denote a part of a register by specifying the
range of bits or by giving a symbol name to a portion of a register.

Registers Transfer Language
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The arrow denotes a transfer of information and the direction of
transfer.
� A comma is used to separate two or more operations that are
executed at the same time.
� T: R2 🡨 R1, R1 🡨 R2

Registers Transfer Language
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The following image shows the block diagram that depicts the transfer of
data from R1 to R2.
� Here, the letter 'n' indicates the number of bits for the register. The 'n'
outputs of the register R1 are connected to the 'n' inputs of register R2.
� A load input is activated by the control variable 'P' which is transferred to
the register R2.

Bus and Memory Transfers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� A typical digital computer has many registers, and paths must be
provided to transfer information from one register to another.
� The number of wires will be excessive if separate lines are used
between each register and all other registers in the system.
� A more efficient scheme for transferring information between
registers in a multiple-register configuration is a common bus
system.
� A bus structure consists of a set of common lines, one for each bit of
a register, through which binary information is transferred one at a
time.
� Control signals determine which register is selected by the bus during
each particular register transfer.

Bus and Memory Transfers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� One way of constructing a common bus system is with multiplexers.
� The multiplexers select the source register whose binary information
is then placed on the bus.
� The construction of a bus system for four registers is shown in Fig.
4-3.
� Each register has four bits, numbered 0 through 3.
� The bus consists of four 4 x 1 multiplexers each having four data
inputs, 0 through 3, and two selection inputs, S1 and S0.
� In order not to complicate the diagram with 16 lines crossing each
other, we use labels to show the connections from the outputs of the
registers to the inputs of the multiplexers.

Bus and Memory Transfers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Bus and Memory Transfers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� For example, output 1 of register A is connected to input 0 of MUX 1
because this input is labeled A1.
� The diagram shows that the bits in the same significant position in
each register are connected to the data inputs of one multiplexer to
form one line of the bus.
� Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1
multiplexes the four 1 bits of the registers, and similarly for the other
two bits.
� The two selection lines S1 and S0 are connected to the selection
inputs of all four multiplexers.
� The selection lines choose the four bits of one register and transfer
them into the four-line common bus.

Bus and Memory Transfers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� When S1S0 = 00, the 0 data inputs of all four multiplexers are
selected and applied to the outputs that form the bus.
� This causes the bus lines to receive the content of register A since the
� outputs of this register are connected to the 0 data inputs of the
multiplexers.

Bus and Memory Transfers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Similarly, register B is selected if S1S0 = 01, and so on. Table 4-2
shows the register that is selected by the bus for each of the four
possible binary value of the selection lines.
� In general, a bus system will multiplex k registers of n bits each to
produce an n-line common bus.
� The number of multiplexers needed to construct the bus is equal to n,
the number of bits in each register.
� The size of each multiplexer must be k x 1 since it multiplexes k data
lines.
� For example, a common bus for eight registers of 16 bits each
requires 16 multiplexers, one for each line in the bus.
� Each multiplexer must have eight data input lines and three selection
lines to multiplex one significant bit in the eight registers.

Bus and Memory Transfers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The transfer of information from a bus into one of many destination
registers can be accomplished by connecting the bus lines to the
inputs of all destination registers and activating the load control of
the particular destination register selected.
� The symbolic statement for a bus transfer may mention the bus or its
presence may be implied in the statement.
� When the bus is includes in the statement, the register transfer is
symbolized as follows:
BUS 🡨 C, R1 🡨 BUS
� The content of register C is placed on the bus, and the content of the
bus is loaded into register R 1 by activating its load control input.
R1 🡨 C

Three State Bus Buffers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� A bus system can be constructed with three-state gates instead of
multiplexers.
� A three-state gate is a digital circuit that exhibits three states.
� Two of the states are signals equivalent to logic 1 and 0 as in a
conventional gate.
� The third state is a high-impedance state.
� The high-impedance state behaves like an open circuit, which means
that the output is disconnected and does not have a logic significance.
� Three-state gates may perform any conventional logic, such as AND
or NAND.
� However, the one most commonly used in the design of a bus system
is the buffer gate.

Three State Bus Buffers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The construction of a bus system with three-state buffers is
demonstrated in Fig. 4-5.
� The outputs of four buffers are connected together to form a single
bus line. (It must be realized that this type of connection cannot be
done with gates that do not have three-state outputs.)

Three State Bus Buffers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� When the control input is equal to 1, the output is enabled and the
gate behaves like any conventional buffer, with the output equal to
the normal input.
� When the control input is 0, the output is disabled and the gate goes
to a high-impedance state, regardless of the value in the normal
input.
� The high-impedance state of a three-state gate provides a special
feature not available in other gates.
� Because of this feature, a large number of three-state gate outputs can
be connected with wires to form a common bus line without
endangering loading effects.

Three State Bus Buffers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The construction of a bus system with three-state buffers is
demonstrated in Fig. 4-5.
� The outputs of four buffers are connected together to form a single
bus line. (It must be realized that this type of connection cannot be
done with gates that do not have three-state outputs.)
� The control inputs to the buffers determine which of the four normal
inputs will communicate with the bus line .
� No more than one buffer may be in the active state at any given time.
� The connected buffers must be controlled so that only one three-state
buffer has access to the bus line while all other buffers are
maintained in a high impedance state.

Three State Bus Buffers
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Three State Bus Buffers
Mr. Mayank Lovanshi mayank.lovanshi@medicaps.ac.in
� One way to ensure that no more than one control input is active at
any given time is to use a decoder, as shown in the diagram.
� When the enable input of the decoder is 0, all of its four outputs are
0, and the bus line is in a high-impedance state because all four
buffers are disabled.
� When the enable input is active, one of the three-state buffers will be
active, depending on the binary value in the select inputs of the
decoder.
� Each group of four buffers receives one significant bit from the four
registers.
� Each common output produces one of the lines for the common bus
for a total of n lines. Only one decoder is necessary to select between
the four registers.

Memory Transfer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The transfer of information from a memory word to the outside
environment is called a read operation.
� The transfer of new information to be stored into the memory is
called a write operation.
� A memory word will be symbolized by the letter M.
� The particular memory word among the many available is selected
by the memory address during the transfer.
� It is necessary to specify the address of M when writing memory
transfer operations.
� This will be done by enclosing the address in square brackets
following the letter M.
� Consider a memory unit that receives the address from a register,
called the address register, symbolized by AR .

Memory Transfer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The data are transferred to another register, called the data register,
symbolized by DR .
� The read operation can be stated as follows:
� Read: DR 🡨 M[AR]
� This causes a transfer of information into DR from the memory word
M selected by the address in AR .
� The write operation transfers the content of a data register to a
memory word M selected by the address.
� Assume that the input data are in register Rl, R2 is the symbol for the
1' s complement of R2.
� Adding 1 to the 1's complement produces the 2's complement.
Adding the contents of R1 to the 2's complement of R2 is equivalent
to R1 - R2.

Memory Transfer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Memory Transfer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The increment and decrement microoperations are symbolized by
plus-one and minus-one operations, respectively.
� These microoperations are implemented with a combinational
circuit or with a binary up-down counter.
� The arithmetic operations of multiply and divide are not listed in
Table 4- 3.
� These two operations are valid arithmetic operations but are not
included in the basic set of microoperations.
� The only place where these operations can be considered as
microoperations is in a digital system, where they are implemented
by means of a combinational circuit.

Memory Transfer
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� In such a case, the signals that perform these operations propagate
through gates, and the result of the operation can be transferred into
a destination register by a clock pulse as soon as the output signal
propagates through the combinational circuit.
� In most computers, the multiplication operation is implemented with
a sequence of add and shift microoperations.
� Division is implemented with a sequence of subtract and shift
microoperations.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The CPU sends various data values, instructions and information to
all the devices and components inside the computer.
� If you look at the bottom of a motherboard you'll see a whole
network of lines or electronic pathways that join the different
components together.
� This network of wires or electronic pathways is called the 'Bus’.
� A bus is a communication pathway connecting two or more devices.
� A key characteristic of a bus is that it is a shared transmission
medium.
� Multiple devices connect to the bus, and a signal transmitted by any
one device is available for reception by all other devices attached to
the bus.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� If two devices transmit during the same time period, their signals
will overlap and become distorted. Thus, only one device at a time
can successfully transmit.
� Typically, a bus consists of multiple communication pathways, or
lines. Each line is capable of transmitting signals representing binary
1 and binary 0.
� Several lines of a bus can be used to transmit binary digits
simultaneously (in parallel).
� For example, an 8-bit unit of data can be transmitted over eight bus
lines.
� Computer systems contain a number of different buses that provide
pathways between components at various levels of the computer
system hierarchy.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 Common Bus system is used to provides the path to transfer data
from register to register or in-between the registers and memory.
 In common bus system diagram there are 7 components (six
registers and a single memory) are connected with a common bus.
So, to represent these seven components of common bus system in
binary, we require three select lines S0, S1, and S2.
 Common Bus System uses a multiplexer to implement Common
BUS.
 Memory and all Registers are connected through a common bus
system.
 We consider 3 select lines (S0, S1, and S2) because we are using 7
inputs to multiplexer as shown in the following diagram. With the
help of 3 select lines, 8 inputs to multiplexer can be given.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 Select lines are 2n. It means how many total inputs can be added.
As 23=8x1(called 8 inputs and one output).
 If inputs are 4 or less than four, then we use two select lines i.e.
S0 and S1.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 6 registers (AR, PC, DR, AC, IR and TR) and memory unit are
connected to common bus.
 The DR (Data Register) is also connected with the ADDER and
Logic Unit to perform operations on data through data Bus.
 INPTR (Input register) is not connected with the common bus.
 It receives data directly for Input device and sends it to Adder and
Logic unit (part of ALU) for operations (+, -,*, /) and then pass it
to Accumulator register.
 The adder and logic unit also contains a carry bit called (E) in case
of addition.
 OUTR (Output Register) does not send data to a common bus or
any other register because it sends directly to the output device but
it receives data from the common bus.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 Every register in the system is connected with Clock Signals.
 Clock Signal controls LD, INR (increment), CLR (Clear register)
commands by the control unit.
 Memory read (R) and writes (W) operation also controlled by
Control Unit.
 Size of Registers In Common Bus System?
 i. The Main memory is of 4096×16 = 2^12 x 16. To represent
4096 (2^12 ) memory we require 12 bits. So 12 bits are required to
address 4096 Memory. X16 means 16 bits word, which will be
access or transfer at a time when we move data from memory to
registers.
 ii. We require a common bus of 16 bits because word size is 16
bits and it has to pass through a common bus.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 iii. AR and PC registers deal with the address of the memory so
their sizes will be 12 bits. When the address of these registers
arrives at a common bus its 4 most significant bits becomes zero.
 iv. DR, AC, IR, and TR register deal with data of memory so there
size will be 16 bits because word size is 16 bits.
 v. Input register (INPR) and the output register (OUTR) send and
receive data character by character, So, 8 bits required for INPR
and OUTR Registers and communicate with 8 least significant bits
in the common bus.
 vi. Select lines bits value depends on how many components are
connected with a common bus. Select lines follow the rule of 2^n
where n is select lines bit value. 2 bits can represent 4 components
(0-3). 3 bits require to represent 8(0-7) and so on.

Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 How Common Bus System Works?
 Step I: Any register can send its data to a common bus by
activating its selected lines (S2, S1, S0).
 Step II: If any register wants to receive data then its LD command
will activate by setting the LD command value to 1. And LD
command of all others registers set to zero.
 Note: Activation/Deactivation of LD, INR or CLR of any register
is done through a circuit called control unit.
 Step III: Main process starts with the program counter.
 Program counter fetches the address of memory which has to
execute. And then pass this address to common bus.
 Other name of DR (data register) are MBR or MDR.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 AR receive the address from common bus by activating its LD
bits. Then AR sends the address to memory directly because AR is
directly connected with common bus. Memory read the address
and sends Data of that address to DR through common Bus.
 Step IV: Memory fetched data will be in DATA Register and then
pass to Accumulator register by Data BUS because DR is directly
connected with AC by Data Bus. Copy of this data is transfer to IR
because when data pass to the accumulator register then Data
Register will flush-out. So that the next incoming data in the next
cycle can store. If the Accumulator register wants to store,
(received data form DR) temporary in somewhere then it passes it
to Temporary register (TR). If we want to retrieve the data from
TR then its data is first loaded in DR and then it passes to AC.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� System Bus
� A bus that connects major computer components (processor,
memory, I/O) is called a system bus.
� A system bus consists, typically, of from about fifty to hundreds of
function.
� System bus usually is separated into three functional groups .
� 1. Data Bus
� 2. Address Bus
� 3. Control Bus
� In addition, there may be power distribution lines that supply power
to the attached modules.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Data Bus
� A collection of wires through which data is transmitted from one
part of a computer to another.
� Data Bus can be thought of as a highway on which data travels
within a computer.
� This bus connects all the computer components to the CPU and
main memory.
� The data bus may consist of 32, 64, 128, or even more separate
lines.
� The number of lines being referred to as the width of the data bus.
Because each line can carry only 1 bit at a time, the number of lines
determines how many bits can be transferred at a time.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� It is a bidirectional bus.
� The size (width) of bus determines how much data can be
transmitted at one time.
� Example:
� A 16-bit bus can transmit 16 bits (2 bytes)of data at a time.
� 32-bit bus can transmit 32 bits(4 bytes) at a time.
� The size (width) of bus is a critical parameter in determining system
performance.
� The wider the data bus, the better, but they are expensive.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Address Bus
� A collection of wires used to identify particular location in main
memory is called Address Bus.
� Or in other words, the information used to describe the memory
locations travels along the address bus.
� Clearly, the width of the address bus determines the maximum
possible memory capacity of the system.
� N address lines directly address 2𝑁memory locations.
� It is an unidirectional bus.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The CPU sends address to a particular memory locations and I/O
ports.
� The address bus consists of 16 , 20 , 24 or more parallel signal lines.
� Some Processors:
� 8086: 20 address lines
� Could address 1 MB of memory
� Pentium: 32 address lines
� Could address 4 GB of memory
� Itanium: 64 address lines
� Could address 264 bytes of memory

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Control Bus
� Because the data and address lines are shared by all components,
there must be a means of controlling their use.
� The control lines regulates the activity on the bus.
� Control signals transmit both command and timing information
among system modules.
� The control bus carries signals that report the status of various
devices.

Common Bus System
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Typical control bus signals are :
� Memory Read : causes data from the addressed location to be
placed on the data bus.
� Memory Write : causes data on the bus to be written into the
addressed location.
� I/O write: causes data on the bus to be output to the addressed I/O
port.
� I/O read: causes data from the addressed I/O port to be placed on
the bus.
� The following figure shows how the CPU reads the value 12 from the
memory location 2453:

Common Bus System – Memory Read
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Common Bus System – Memory Read
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� CPU sends out the address value 2453 on the address bus.
� Simultaneously, CPU sends out the signal R/W = 1 on the control
bus, which indicates a READ operation.
� CPU then waits for the data from memory on the data bus.
� The R/W = 1 signal and the address bus value 2453 will cause the
memory to retrieve the value at memory location 2453 to be sent out
on the data bus.

Common Bus System – Memory Read
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Address of next instruction is in PC
� Address (MAR) is placed on address bus
� Control unit issues READ command
� Result (data from memory) appears on data bus
� Data from data bus copied into MBR
� PC incremented by 1 .
� Data (instruction) moved from MBR to IR
� MBR is now free for further data fetches

Common Bus System – Memory Write
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� CPU sends out the address value 2453 on the address bus.
� Simultaneously, CPU also sends out the value 53 on the data bus.
� And the signal R/W = 0 on the control bus which indicating a
WRITE operation.
� The R/W = 0 signal along with the address bus value 2453 and data
bus value 53 will cause the memory to store the value 53 at the
location 2453...
� The following figure shows how the CPU writes the value 53 from
the memory location 2453:

Common Bus System – Memory Write
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
� Machine Instructions are commands or programs written in machine
code of a machine (computer) that it can recognize and execute.
� A machine instruction consists of several bytes in memory that tells
the processor to perform one machine operation.
� The processor looks at machine instructions in main memory one
after another, and performs one machine operation for each machine
instruction.
� The collection of machine instructions in main memory is called
a machine language program.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
� Machine code or machine language is a set of instructions executed
directly by a computer’s central processing unit (CPU).
� Each instruction performs a very specific task, such as a load, a
jump, or an ALU operation on a unit of data in a CPU register or
memory.
� Every program directly executed by a CPU is made up of a series of
such instructions.
� The general format of a machine instruction is
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
[Label:] Mnemonic [Operand, Operand] [; Comments]

Machine Instruction
• Brackets indicate that a field is optional.
• Label is an identifier that is assigned the address of the first byte of
the instruction in which it appears. It must be followed by “:”
• Inclusion of spaces is arbitrary, except that at least one space must
be inserted; no space would lead to an ambiguity.
• Comment field begins with a semicolon “ ; ”
• Example
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Here: MOV R5,#25H ;load 25H into R5

Machine Instruction
� 1. Data transfer instructions– move, load exchange, input, output.
• MOV : Move byte or word to register or memory .
• IN, OUT: Input byte or word from port, output word to port.
• LEA: Load effective address
• LDS, LES: Load pointer using data segment, extra segment .
• PUSH, POP: Push word onto stack, pop word off stack.
• XCHG: Exchange byte or word.
• XLAT: Translate byte using look-up table.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
� 2. Arithmetic instructions – add, subtract, increment, decrement, convert
byte/word and compare.
• ADD, SUB: Add, subtract byte or word
• ADC, SBB : Add, subtract byte or word and carry (borrow).
• INC, DEC: Increment, decrement byte or word.
• NEG: Negate byte or word (two’s complement).
• CMP: Compare byte or word (subtract without storing).
• MUL, DIV: Multiply, divide byte or word (unsigned).
• IMUL, IDIV: Integer multiply, divide byte or word (signed)
• CBW, CWD: Convert byte to word, word to double word
• AAA, AAS, AAM,AAD: ASCII adjust for add, sub, mul, div .
• DAA, DAS: Decimal adjust for addition, subtraction (BCD
numbers)
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
� 3. Logic instructions – AND, OR, exclusive OR, shift/rotate and test
• NOT : Logical NOT of byte or word (one’s complement)
• AND: Logical AND of byte or word
• OR: Logical OR of byte or word.
• XOR: Logical exclusive-OR of byte or word
• TEST: Test byte or word (AND without storing).
• SHL, SHR: Logical Shift rotate instruction shift left, right byte or
word? by 1or CL
• SAL, SAR: Arithmetic shift left, right byte or word? by 1 or CL
• ROL, ROR: Rotate left, right byte or word? by 1 or CL .
• RCL, RCR: Rotate left, right through carry byte or word? by 1 or
CL.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
4. String manipulation instruction – load, store, move, compare and
scan for byte/word.
• MOVS: Move byte or word string.
• MOVSB, MOVSW: Move byte, word string.
• CMPS: Compare byte or word string.
• SCAS S: can byte or word string (comparing to A or AX).
• LODS, STOS: Load, store byte or word string to AL.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
5. Control transfer instructions – conditional, unconditional, call
subroutine and return from subroutine.
• JMP: Unconditional jump .it includes loop transfer and subroutine
and interrupt instructions.
• JNZ: jump till the counter value decreases to zero. It runs the loop
till the value stored in CX becomes zero.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
6. Loop control instructions-
• LOOP: Loop unconditional, count in CX, short jump to target
address.
• LOOPE (LOOPZ): Loop if equal (zero), count in CX, short jump to
target address.
• LOOPNE (LOOPNZ): Loop if not equal (not zero), count in CX,
short jump to target address.
• JCXZ: Jump if CX equals zero (used to skip code in loop).
• Subroutine and Intrrupt instructions-
• CALL, RET: Call, return from procedure (inside or outside current
segment).
• INT, INTO: Software interrupt, interrupt if overflow.IRET: Return
from interrupt.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
7. Processor control instructions-
� Flag manipulation:
• STC, CLC, CMC: Set, clear, complement carry flag.
• STD, CLD: Set, clear direction flag.STI, CLI: Set, clear interrupt
enable flag.
• PUSHF, POPF: Push flags onto stack, pop flags off stack.
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Concept of Program Execution
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Machine Instruction
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Program Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The next consideration for architecture design concerns how the
CPU will store data.
� We have three choices:
� 1. A stack architecture
� 2. An accumulator architecture
� 3. A general purpose register architecture.
� In choosing one over the other, the tradeoffs are simplicity (and
cost) of hardware design with execution speed and ease of use.

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� In a stack architecture, operands are implicitly taken from the stack.
� A stack cannot be accessed randomly.
� In an accumulator architecture, one operand of a binary operation is
implicitly in the accumulator.
� One operand is in memory, creating lots of bus traffic.
� In a general purpose register (GPR) architecture, registers can be
used instead of memory.
� Faster than accumulator architecture.
� Efficient implementation for compilers.
� Results in longer instructions.

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Most systems today are GPR systems.
� There are three types:
� Memory-memory where two or three operands may be in memory.
� Register-memory where at least one operand must be in a register.
� Load-store where only the load and store instructions can access
memory.
� The number of operands and the number of available registers has a
direct affect on instruction length.

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� A basic computer has three instruction code formats which are:
� Memory - reference instruction
� Register - reference instruction
� Input-Output instruction
� Memory Reference – These instructions refer to memory address
as an operand. The other operand is always accumulator. Specifies
12-bit address, 3-bit opcode (other than 111) and 1-bit addressing
mode for direct and indirect addressing.

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Register Reference – These instructions perform operations on
registers rather than memory addresses.
� The IR(14 – 12) is 111 (differentiates it from memory reference) and
IR(15) is 0 (differentiates it from input/output instructions).
� The rest 12 bits specify register operation.
� The Register-reference instructions are represented by the Opcode
111 with a 0 in the leftmost bit (bit 15) of the instruction.

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Input/Output – These instructions are for communication between
computer and outside environment.
� The IR(14 – 12) is 111 (differentiates it from memory reference) and
IR(15) is 1 (differentiates it from register reference instructions).
� The rest 12 bits specify I/O operation.
� Note: The Operation code (Opcode) of an instruction refers to a
group of bits that define arithmetic and logic operations such as add,
subtract, multiply, shift, and compliment.

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Instruction is command which is given by the user to computer.
� The time period during which one instruction is fetched from
memory and execute when a computer given an instruction in
machine language.
� Each instruction is further divided into sequence of phases.
� After the execution the program counter is incremented to point to
the next instruction.
� Phases:
� Fetch an instruction from memory
� Decode the instruction
� Execute the instruction

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle – State Diagram
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Cycle
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The Instruction Set Architecture (ISA) is the part of the processor
that is visible to the programmer or compiler writer.
� The ISA serves as the boundary between software and hardware.
� The ISA of a processor can be described using 5 catagories:
� Operand Storage in the CPU
� Where are the operands kept other than in memory?
� Number of explicit named operands
� How many operands are named in a typical instruction.
� Operand location
� Can any ALU instruction operand be located in memory? Or must
all operands be kept internaly in the CPU?

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Operations
� What operations are provided in the ISA.
� Type and size of operands
� What is the type and size of each operand and how is it specified?
� The 3 most common types of ISAs are:
� Stack - The operands are implicitly on top of the stack.
� Accumulator - One operand is implicitly the accumulator.
� General Purpose Register (GPR) - All operands are explicitly
mentioned, they are either registers or memory locations.
� Lets look at the assembly code of in all 3 architectures:
C = A + B;

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Earlier CPUs were of the first 2 types but in the last 15 years all
CPUs made are GPR processors.
� The 2 major reasons are that registers are faster than memory, the
more data that can be kept internally in the CPU the faster the
program will run.
� The other reason is that registers are easier for a compiler to use.
Stack Accumulator GPR
PUSH A LOAD A LOAD R1,A
PUSH B ADD B ADD R1,B
ADD STORE C STORE R1,C
POP C - -

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Instruction set architectures are measured according to:
� Main memory space occupied by a program.
� Instruction complexity.
� Instruction length (in bits).
� Total number of instructions in the instruction set.
� Stack machines use one- and zero-operand instructions.
� PUSH and POP instructions require a single memory address
operand.
� PUSH and POP operations involve only the stack’s top element.
� Other instructions use operands from the stack implicitly.
� Binary instructions (e.g., ADD, MULT) use the top two items on the
stack.

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Stack architectures require us to think about
� arithmetic expressions a little differently.
� We are accustomed to writing expressions using infix notation, such
as: Z = X + Y.
� Stack arithmetic requires that we use postfix notation:
Z = XY+.
� This is also called reverse Polish notation, (somewhat) in honor of
its Polish inventor, Jan Lukasiewicz (1878 - 1956).
� The principal advantage of postfix notation is that parentheses are
not used.

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� For example, the infix expression,
� Z = (X × Y) + (W × U)
� becomes:
� Z = X Y × W U × +
� in postfix notation.
� Example: Convert the infix expression (2+3) - 6/3 to postfix:
� 2 3 + 6 3 / -

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Example: Use a stack to evaluate the postfix expression 2 3 + 6 3 / -

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Example: Use a stack to evaluate the postfix expression 2 3 + 6 3 / -

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Example: Use a stack to evaluate the postfix expression 2 3 + 6 3 / - :

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Example: Use a stack to evaluate the postfix expression 2 3 + 6 3 / - :

Instruction Set Architecture
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Example: Use a stack to evaluate the postfix expression 2 3 + 6 3 / - :

Types of Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Instruction Formats (Zero, One, Two and Three Address
Instruction).
� Computer perform task on the basis of instruction provided.
� An instruction in computer comprises of groups called fields.
� These field contains different information as for computers every thing is
in 0 and 1 so each field has different significance on the basis of which a
CPU decide what to perform.
� The most common fields are:
� Operation field which specifies the operation to be performed like
addition.
� Address field which contain the location of operand, i.e., register or
memory location.
� Mode field which specifies how operand is to be founded.

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 Let’s see how to evaluate an infix expression using different
instruction formats.
 Assume U,W,X,Y & Z are memory address.
 With a three-address ISA, (e.g.,mainframes), the infix expression,
 Z = X × Y + W × U
 might look like this:
 MULT R1,X,Y
 MULT R2,W,U
 ADD Z,R1,R2

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 In a two-address ISA, (e.g.,Intel, Motorola), the infix expression,
 Z = X × Y + W × U
 might look like this:
 LOAD R1,X
 MULT R1,Y
 LOAD R2,W
 MULT R2,U
 ADD R1,R2
 STORE Z,R1
 Note: One-address ISAs usually require one operand to be a register.

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 In a one-address ISA, like MARIE, (Accumulator based CPU)
 the infix expression,
 Z = X × Y + W × U
 looks like this:
 LOAD X
 MULT Y
 STORE TEMP
 LOAD W
 MULT U
 ADD TEMP
 STORE Z

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
 In a stack ISA, (Stack based CPU) the postfix expression, (First Operand then
Operator) Z = X Y × W U × +
 PUSH X
 PUSH Y
 MUL
 PUSH W
 PUSH U
 MUL
 ADD
 POP Z
 Note: The result of a binary operation is implicitly stored on the top of the stack.

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Question:- Write a program to evaluate the arithmetic statement:
� X= A-B+C*(D*E-F)/G+H*K
� a)Using a general register computer with three address instructions
� b)Using a general register computer with two address instructions
� c)Using an accumulator type computer with one address instructions
� d)Using a stack organizer computer with zero-address operation instructions.

Instruction Format
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Numerical Problems
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Q.1 A new computer system has a 3 GHz processor with a 64-bit data bus and a
32-bit address bus. Calculate the maximum amount of memory that can be
addressed by this computer. Show all your working and express your answer in
appropriate units.
� Maximum amount of addressable memory = 2address bus X data bus
� = 232X 64
� = 274 877 906 944 bits
� = 34 359 738 368 bytes
� = 33 554 432 KB = 32768 MB = 32 GB

Numerical Problems
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� A computer has a 24-bit data bus, a 32-bit address bus and a 16 line control bus.
Calculate the maximum amount of memory that can be addressed by this
computer. Show all your working and express your answer in appropriate units.
� Maximum amount of addressable memory = 2address bus X data bus
� = 232 X 24
� = 103 079 215 104 bits
� = 12 884 901 888 Bytes
� = 12 582 912 KB
� = 12 288 MB
� = 12 Gigabytes

Numerical Problems
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� The Phantom IV has a 32-bit data bus and a 24-bit address bus. Calculate the
amount of memory which the Phantom IV can address. Give your answer in
appropriate units. Show all working.
� Maximum amount of addressable memory = 2address bus X data bus
� = 224 X 32
� = 1 073 741 824 bits
� = 67 108 864 Bytes
� = 65 536 KB
� = 64 MB

Numerical Problems
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Q. A machine has 24 bit instruction format. It has 32 bit registers and each of
which is 32 bit long. It needs to support 49 instructions. Each instruction has
two register operands and one immediate operand . If the immediate operand is
signed integer, the minimum value of immediate operand is . . . . . . . . . . .
� Sol: 49 instruction = 6 bit needed for op-code
� 32 registers = 5 bits needed for register operands
� 2 register operands, therefore 10 bits.
� instruction size= 24 bits
� immediate operand bits= instruction size - (opcode + register operand)
� Immediate operand bits = 8
� signed value= -(2^(n-1) - 1)
� Minimum value = -2^7 -1= -127

Numerical Problems
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Q.2 A machine has a 32-bit architecture, with 1-word long
instructions. It has 64 registers, each of which is 32 bits long. It
needs to support 45 instructions, which have an immediate operand
in addition to two register operands. Assuming that the immediate
operand is an unsigned integer, the maximum value of the immediate
operand is ____________.

Unit – 1
Any - 5 Assignment Questions Marks:-20
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in
� Q.1 Draw and explain the functional block diagram of Von Neumann model.
� Q.2 Explain working of the System bus in a computer system. How CPU
Perform Memory Read and Memory Write using system bus.
� Q.3 What is Instruction cycle? Explain different phases of instruction cycle
and show flow chart for instruction cycle.
� Q.4 Define Register transfer language? Explain the different types of register
transfer language.
� Q.5 Write a program to evaluate the arithmetic statement:
X= A-B+C*(D*E-F)/G+H*K
� Q.6 Explain the purpose of General register, Memory register and instruction
register with example.
� Q.7 Describe the function of Control unit and ALU.

Questions
Mr. Sagar Pandya sagar.pandya@medicaps.ac.in

Thank You
Great God, Medi-Caps, All the attendees
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sagar.pandya@medicaps.ac.in
www.sagarpandya.tk
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Mr. Sagar Pandya sagar.pandya@medicaps.ac.in