1. 80386 Microprocessor
Presented By,
Er. Swapnil Kaware,
B.E.(Electronics),
svkaware@yahoo.co.in
1

2. Salient Features Of 80386 Microprocessor
(1). 80386 Microprocessor Introduced in 1985 by Intel Corporation.
(2). Address bus is of 32-bit & Data bus is of 32-bit.
(3). 80386 Microprocessor can address up to 232 i.e. 4G bytes of memory.
(4). Operating frequency of 20-33 MHz .
(5). Contains total 132 Pins.
(6). Intel’s first practical microprocessor to contain a 32-bit data bus and 32-bit memory
address
(7). 80386 had higher clocking speeds and included a memory management unit.
(8). Improved efficiency, reduced software overload.
(9). Instruction set, memory management upward-compatible with 8086, 8088, and 80286
Microprocessor.
(10). Can operates in real, protected & virtual Mode.
(11). Introduced paging, virtual memory concept.
(12). Based on CMOS Technology.
(13). Contains near about 2,75,000 Transistors.
(14). Can operate at 11.4 MIPS.
(15). 11 Addressing modes.
2

3. Versions of 80386 Microprocessor
(A) 80386 SX (B) 80386 DX
(1). A.B. is of 32 Bit. (1). A.B. is of 24 Bit.
(2). D.B. is of 32 Bit. (2). D.B. is of 16 Bit.
(3). Total 132 Pins. (3). Total 100 Pins.
(4). Can address upto (4). Can address upto
4GB of memory. 16MB of memory.
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4. Register Organization Of 80386
4

5. Register Organization Of 80386
(1). The 80386 has eight 32 - bit general purpose registers which may be used as
either 8 bit or 16 bit registers.
(2). A 32 - bit register known as an extended register, is represented by the register
name with prefix E.
(3). Example : A 32 bit register corresponding to AX is EAX, similarly BX is EBX etc.
(4). The 16 bit registers BP, SP, SI and DI in 8086 are now available with their
extended size of 32 bit and are names as EBP,ESP,ESI and EDI.
(5). AX represents the lower 16 bit of the 32 bit register EAX.
(6). BP, SP, SI, DI represents the lower 16 bit of their 32 bit counterparts, and can be
used as independent 16 bit registers.
(7). The CS and SS are the code and the stack segment registers respectively, while
DS, ES, FS, GS are 4 data segment registers.
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6. Flag Register of 80386 Microprocessor
• The Flag register of 80386 is a 32 bit register. Out of the 32 bits, Intel has
reserved bits D18 to D31, D5 and D3, while D1 is always set at 1.
• Two extra new flags are added to the 80286 flag to derive the flag register of
80386. They are VM and RF flags.
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7. Flag Register of 80386 Microprocessor
(1). IOPL (Input Output Privilege Level) flags:- For protected mode operations
indicates the privilege level, 0 to 3, at which your code must be running in
order to execute any I/O-related instructions.
(2). VM Virtual 8086 mode flag:- When it is set, the x86 processor is basically
converted into a high-speed 8086 processor.
(3). RF:- Resume Flag This flag is used with the debug register break points. It is
checked at the starting of every instruction cycle.
• The RF is automatically reset after successful execution of every instruction.
(4). NT :- (Nested Task) The processor uses the nested task flag to control chaining
of interrupted and called tasks.
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8. VM - Virtual Mode Flag
• If this flag is set, the 80386 enters the virtual
8086 mode within the protection mode.
• This is to be set only when the 80386 is in
protected mode.
• This bit can be set using IRET instruction or any
task switch operation only in the protected
mode. 8

9. RF- Resume Flag
• It is checked at the starting of every instruction cycle and if it
is set, any debug fault is ignored during the instruction cycle.
• The RF is automatically reset after successful execution of
every instruction, except for IRET and POPF instructions.
• JMP, CALL and INT instructions are used to set the RF to the
value specified by the memory data available at the stack.
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10. • Segment Descriptor Registers:
 This registers are not available for programmers, rather they are
internally used to store the descriptor information, like attributes,
limit and base addresses of segments.
 The six segment registers (i.e. CS,SS,DS,ES,FS,GS) have
corresponding six 73 bit descriptor registers. Each of them contains
32 bit base address, 32 bit base limit and 9 bit attributes.
 These are automatically loaded when the corresponding segments
are loaded with selectors.
• Control Registers:
 The 80386 has three 32 bit control registers CR0, CR2 and CR3
Load and store instructions are available to access these registers.
10

11. • System Address Registers:
• The 80386 supports four types of descriptor table, viz.
(1) Global Descriptor Table (GDT),
(2) Interrupt Descriptor Table (IDT),
(3) Local Descriptor Table (LDT),
(4) Task State Segment Descriptor (TSS).
• They holds the addresses of corresponding segments.
11

12. Debug and Test Registers
32 0
Linear Breakpoint Address 0 DR0
Linear Breakpoint Address 1 DR1
Linear Breakpoint Address 2
DR2
Linear Breakpoint Address 3 DR3
Intel Reserved DR4
Intel Reserved DR5
Breakpoint Status DR6
Breakpoint Control DR7
32 0
Test Control TR6
Test Status TR7
12

13. • Debug and Test Registers:
• Intel has provide a set of 8 debug registers for hardware debugging.
• Out of these eight registers DR0 to DR7, two registers DR4 and DR5 are
Intel reserved.
• The initial four registers DR0 to DR3 store four program controllable
breakpoint addresses, while DR6 and DR7 respectively hold breakpoint
status and breakpoint control information.
• Two more test register are provided by 80386 for page cacheing namely
test control and test status register. 13

14. Addressing Modes
• 80386 supports total 11 addressing modes.
• Scaled Indexed Mode: Contents of the an index register are multiplied by a
scale factor (the valid scale factors are 1,2,4 & 8) that may be added further to
get the operand offset.
e.g. MOV EBX, LIST [ESI*2]
• Based Scaled Indexed Mode: Contents of the an index register are multiplied by
a scale factor and then added to base register to obtain the offset.
e.g. MOV EBX, LIST [EDX*4] [ECX]
• Based Scaled Indexed Mode with Displacement: The Contents of the an index
register are multiplied by a scaling factor and the result is added to a base
register and a displacement to get the offset of an operand.
e.g. MOV EAX, LIST [ESI*2] [EBX+0800]
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15. Data Types Of 80386
(1). Bit.
(2). Bit field-A group of at most 32 bits i.e., 4 bytes.
(3). Bit string- A string of continuous bits of maximum 4Gbytes length.
(4). Signed Byte- Signed byte data. Sign of the operand depends upon its most
significant bit. If it is 0, then the number is positive. else it is negative. Range
is from -128 to 127.
(5). Unsigned Byte-Unsigned byte data.Range from 0 to 255.
(6). Integer word- Signed 16-bit data. Range from -32,768 to 32,767.
(7). Long Integer-32-bit signed data that is represented in 2's complement form.
Range is from -2.147*109 to 2.1479.
(8). Unsigned Integer Word- Unsigned 16-bit data.Range from 0 to 65,535.
(9). Unsigned Long Integer-Unsigned 32 bit data. Range from 0 to 4,294,967,295.
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16. (10). Signed quad word- A signed 64-bit or four word data.
(11). Unsigned Quad Word-An unsigned 64-bit data.
(12). Offset-A 16 or 32- bit displacement that references a memory location using
any of the addressing modes.
(13). Pointer-16-bit selector and 16 or 32 bit offset.
(14). Character-An ASCII equivalent to any of the alphanumeric or control
characters .
(15). Strings-These are the sequences of bytes, words or double words . A string
may contain up to maximum 4 GB.
(16). BCD- Decimal digits from 0-9 represented by unpacked bytes.
(17). Packed BCD- This represents two packed BCD digits using a byte from 00 to
99.
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17. Real Addressing Mode
(1). After reset, the 80386 starts from memory location FFFFFFF0H under the real address
mode.
(2). In the real mode, 80386 works as a faster 8086 with 32-bit registers and data types.
(3). In real mode, the default operand size is 16 bit but 32- bit operands and addressing
modes may be used.
(4). The segment size in real mode is 64K.
(5). The real mode initializes the 80386 and prepares it for protected mode.
(6). The segments in 80386 real mode may be overlapped or non-overlapped.
(7). The segment in 80386 real mode can be read, write or executed, i.e. no protection is
available.
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18. 18

19. Protected Mode of 80386
(1). All the capabilities of 80386 are available for utilization in its protected mode of
operation.
(2). The 80386 in protected mode support all the software written for 80286 and 8086 to
be executed under the control of memory management and protection abilities of
80386.
(3). The protected mode allows the use of additional instruction, addressing modes and
capabilities of 80386.
(4). The effective address (offset) is added with segment base address to calculate linear
address.
(5). This linear address is further used as physical address, if the paging unit is disabled,
otherwise the paging unit converts the linear address into physical address.
(6). The paging unit operates under the control of segmentation unit. The paging unit if
enabled converts linear addresses into physical address, in protected mode.
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20. Segmentation
DESCRIPTOR TABLES:
These descriptor tables and registers are manipulated by the operating
system to ensure the correct operation of the processor, and hence the
correct execution of the program. Three types of the 80386 descriptor
tables are listed as follows:
(1). GLOBAL DESCRIPTOR TABLE ( GDT )
(2). LOCAL DESCRIPTOR TABLE ( LDT )
(3). INTERRUPT DESCRIPTOR TABLE ( IDT )
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21. • GDT
(1). Maintains list of Most Segments
(2). It’s a general Purpose table of descriptors.
(4). 48-bit register.
• IDT
(1). Maintains list of Interrupt service routines.
(2). 48-bit register.
• LDT
(1) Optional.
(2) Extends range of GDT.
(3) Is allocated to each task when multitasking is enabled.
(4). 16-bit register.
21

22. Segment Descriptor Format
(1). A ( Accessed) : Processor automatically sets this bit whenever a memory
reference is made using the defined segment .
(2). DPL : Indicates the level of privilege associated with the memory space that
descriptor defines. DPL0 is highest while DPL3 is lowest.
(3). S ( System ) : If clear indicates that this is system segment descriptor. If set non-
system.
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23. (4). P ( Present): If clear, the address range that this descriptor defines is considered to be
temporarily not present in physical memory space.
(5). U ( User): Undefined and ignored by 80386,but user can use it.
(6). X : Reserved
(7). D ( Default):When clear operands in this is segment is assumed to be 16 bits and when set
assumed to be 32 bits.
(8). G ( Granularity): When this bit is cleared ,the 20 bit limit field is assumed to be measured in
units of 1 byte. If set the limit is in units of 4 KB.
(9) Type (3): Type of segment you are defining.
(a). 000: Data , read only ( ROM space)
(b). 001: Data ,R/W
(c). 010: Stack read only
(d). 011: Stack R/W
(e). 100: Code, execute only
(f). 101: Code execute/ read
(g). 110: Code execute only , conforming
(h). 111:Code execute / read, conforming 23

24. Paging
(1). Paging is one of the memory management techniques used for
virtual memory multitasking operating system.
(2). The segmentation scheme may divide the physical memory into
a variable size segments but the paging divides the memory into
a fixed size pages.
(3). The segments are supposed to be the logical segments of the
program, but the pages do not have any logical relation with the
program.
(4). The pages are just fixed size portions of the program module or
data. 24

25. (5). The advantage of paging scheme is that the complete segment of a task need
not be in the physical memory at any time.
(6). Only a few pages of the segments, which are required currently for the
execution need to be available in the physical memory.
(7). Thus the memory requirement of the task is substantially reduced,
relinquishing the available memory for other tasks.
(8). Whenever the other pages of task are required for execution, they may be
fetched from the secondary storage.
(9). The previous page which are executed, need not be available in the memory,
and hence the space occupied by them may be relinquished for other tasks.
(10). Thus paging mechanism provides an effective technique to manage the
physical memory for multitasking systems.
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26. 26

27. Paging Unit:
(1). The paging unit of 80386 uses a two level table mechanism to convert a linear address
provided by segmentation unit into physical addresses.
(2). The paging unit converts the complete map of a task into pages, each of size 4K.
(3). The task is further handled in terms of its page, rather than segments.
(4). The paging unit handles every task in terms of three components namely page directory,
page tables and page itself.
Page Directory:
(1). This is at the most 4Kbytes in size. Each directory entry is of 4 bytes, thus a total
of 1024 entries are allowed in a directory.
(2). The upper 10 bits of the linear address are used as an index to the corresponding
page directory entry. The page directory entries point to page tables.
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28. Page Tables:
(1). Each page table is of 4Kbytes in size and many contain a maximum of 1024
entries.
(2). The page table entries contain the starting address of the page and the
statistical information about the page.
(3). The upper 20 bit page frame address is combined with the lower 12 bit of the
linear address.
(4). The accessed bit A is set by 80386 before any access to the page. If A=1, the
page is accessed, else unaccessed.
(5). The D bit ( Dirty bit) is set before a write operation to the page is carried out.
(6). The OS reserved bits are defined by the operating system software.
(7). The User / Supervisor (U/S) bit and read/write bit are used to provide
protection.
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29. Virtual 8086 Mode
(1). Thus, the virtual 8086 mode of operation of 80386, offers an advantage of executing 8086
programs while in protected mode.
(2). The address forming mechanism in virtual 8086 mode is exactly identical with that of 8086 real
mode.
(3). In virtual mode, 8086 can address 1Mbytes of physical memory that may be anywhere in the
4Gbytes address space of the protected mode of 80386.
(4). Like 80386 real mode, the addresses in virtual 8086 mode lie within 1Mbytes of memory.
(5). In virtual mode, the paging mechanism and protection capabilities are available at the service of
the programmers.
(6). The 80386 supports multiprogramming, hence more than one programmer may be use the CPU at
a time.
(7). Paging unit may not be necessarily enable in virtual mode, but may be needed to run the 8086
programs which require more than 1Mbyts of memory for memory management function.
(8). In virtual mode, the paging unit allows only 256 pages, each of 4Kbytes size.
(9). Each of the pages may be located anywhere in the maximum 4Gbytes physical memory.
(10). The virtual mode allows the multiprogramming of 8086 applications.
29

30. 80486 Microprocessor
(1). Introduced in 1989.
(2). Can execute around 40 million instructions per second.
(3). On chip floating point unit for faster execution of complex instructions.
(4). Having operating frequency of 16MHz to 50MHz.
(5). Total 168 pins.
(6). Paging & Virtual memory concept.
(7). Multiprocessor support.
(8). Data bus is of 32 bits.
(9). Address bus is of 32 bits.
(10). High speed data transfer.
(11). More than 1.2 million transistors.
(12). Can address up to 4 billion bytes of memory.
(13). Can operate in real & protected mode.
(14). Contains 80387 arithmetic co processor.
(15). Uses Pipelining i.e. can execute up to 1 instruction per clock cycle.
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31. Flag Register of 80486 Microprocessor
FLAGS
31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
E
F RESERVED FOR
L INTEL AC VM RF 0 NT IOPL OF DF IF TF SF ZF 0 AF 0 PF 1 CF
A
G
CF: Carry Flag
AF: Auxiliary carry
OF : Over Flow
ZF: Zero Flag
IOPL : I/O Privilege Level
SF : Sign Flag
NT : Nested Task Flag
TF : Trap Flag RF : Resume Flag
IE : Interrupt Enable VM : Virtual Mode
AC : Alignment Check
DF : Direct Flag
31

32. Flag Register of 80486
(1). The register set of 80486 is similar to that of 80386.
(2). Only a flag called alignment flag is added at the
position D18.
(3). If the AC flag is set to ’1’, whenever there is an access
to a misaligned address i.e. a fault (exception) is
generated.
32

33. 80586 (Pentium) Microprocessor
(1). Pentium (80586) Microprocessor was introduced in 1993.
(2). Data bus is of 64-bit & address bus is of 32 bits.
(3). Superscalar performance: can execute 2 instructions per clock cycle.
(4). Introductory versions operated with a clocking frequency of 60 MHz & 66 MHz.
(5). Can address up to 4G bytes of memory.
(6). Contains total 237 pins.
(7). Memory access time near about 18 ns.
(8). Contains near about 3.1 millions of transistors.
(9). High-level system functions such as power management and security.
(10). Allows 4MByte memory pages instead of the 4KByte pages.
(11). The numeric coprocessor operates at about five times faster than the 80486 numeric
coprocessor.
(12). A dual-integer processor often allows two instructions per clock.
(13). Super pipelined architecture.
(14). Having speed of 110 MIPs.
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34. Register Organization Of Pentium
(80586) Processor
• Four 32-bit registers can be used as
• Four 32-bit register (EAX, EBX, ECX, EDX)
• Four 16-bit register (AX, BX, CX, DX)
• Eight 8-bit register (AH, AL, BH, BL, CH, CL, DH, DL)
• Some registers have special use ECX for count in loop instructions,
34

35. Register Organization Of Pentium
Processor
35

36. Flag Register of Pentium Processor
36

37. Flag Register of Pentium Processor
(1). ID:- The identification flag is used lb test for the CPUID
instruction. If a program can set and clear the ID flag, the
processor supports the CPUID instruction.
(2). VIP:- Virtual interrupt pending indicates that a virtual interrupt
is pending.
(3). VIF :- Virtual interrupt is the image of the virtual interrupt flag
IF used with VIP.
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38. END OF
SESSION
svkaware@yahoo.co.in 38