1. H igh P erformance P rocessors and S ystems PdM – UIC joint master 2007 Instructor: Prof. Donatella Sciuto HPPS @ PdM – June 2007

3. DRESD in a Nutshell D ynamic R econfigurability in E mbedded S ystem D esign DRESD @ PdM – June 2007

7. SoC Reconfiguration f i x Partial Total Embedded

8. Different Scenarios... Single Device Distributed System

10. D ynamic Re configurability A pplied to M ulti-FPGA S ystems

12. Multi-FPGA Partitioning Alessandro Panella [email_address]

26. Results 3/3

28. The end ANY QUESTIONS?

30. Chimera Multi-FPGAs Architecture Definition Matteo Murgida [email_address]

44. Questions

46. O perating Sy stem support for R econf i gurable S oC

47. Development of an OS architecture-independent layer for dynamic reconfiguration Ivan Beretta [email_address]

62. Questions

64. Design FLow Antonio Piazzi [email_address]

71. Sel f Reconfigurable Architecture

73. Second Phase 2/4 ArchGen take the system.vhd file and process the contained architecture and translate that static architecture in a dynamic one FIX.VHD contains the instantiations of the processors (one or more) and all the components presented in the IBM core-connect architecture TOP.VHD contains the instantiations of the fix component and the information about the communication infrastructure

74. Second Phase 3 /4 COMiC generate an NCD file which contains the information about the communication infrastructure and an XDL file which contains the same information in text mode

75. Second Phase 4/ 4 At this point we have only to collect all the information we need and so, through a parser we insert those into a new top.vhd which will be our fix part of the architecture, at this point we have only to manage the reconfigurable modules written by the user

76. Third Phase 1/3 An OPB bus based on 3-state buffer used to link one or more modules to the fix part (created with ISE) Definition of a new communication infrastructure and transfer protocol for the reconfigurable part

77. Third Phase 2/3 Use ncd2xdl converter to obtain an xdl file which contains all parameters of our bus

78. Third Phase 3/3 Perfect integration in our process, we can use all bus type to connect fix and reconfigurable part Verify the integration of the new infrastructure in the project

81. Questions?

83. Polaris

85. Management of 2D Reconfiguration in a Reconfigurable System Massimo Morandi [email_address]

97. The Placement Algorithm

100. Questions?

102. Relocation for 2D Reconfigurable Systems Marco Novati [email_address]

108. New Parser

111. Target Device

112. Validation Architecture

116. Questions

118. H igh L evel R econfiguration Marco Maggioni marco.maggioni @dresd.org

133. Questions