1. Management and analysis of bitstream generators for Xilinx FPGAs BY Davide Candiloro [email_address] Thesis committee: John Lillis (chair), Marco D. Santambrogio, Piotr Gmytrasiewicz UIC Thesis Defense

6. Xilinx FPGAs and Configuration Memory

15. The proposed Flow and Framework: Rebit C++ wxWidgets

19. Implementation: area retrieval (1)

22. Implementation: area retrieval (2) SLICE X0Y0–X20Y41

24. Conflict Graph Conflict graph conflict=edge Incidence Matrix conflict=red which functionalities can be used at the same time?

25. Design Alteration Module Allows the user to perform modifications to the design 1) Redefining Reconfigurable Regions 2) Relocating partial bitstreams

31. Performance analysis (1)

33. Performance analysis

35. Performance analysis

38. Case study: constraint validation

39. Case study: UCF editing

41. Case study : data model Conflict graph Feasible static photos Aim is to resolve every conflict within each of the static photos

42. Case study: area conflicts

47. Questions? Thank you