VLSI IEEE projects for M.Tech , B.Tech . Publications also Done by us feel free to Contact us .

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VLSI M.TECH & B.TECH PROJECT LIST 2015-2016
SL.NO YEAR TITLE
1 2014 T
32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling
Multiplier With Operands Scheduler.
2 2014 T
A parallel radix-sort-based VLSI architecture for finding the first W
maximum/minimum values.
3 2014 T
Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter
With Low Adaptation-Delay.
4 2014 T
Data encoding techniques for reducing energy consumption in
NOC.
5 2014 T
Fully reused VLSI architecture of FM0/Manchester encoding
using SOLS technique for DSRC applications.
6 2014 T
Low complexity low latancy architecture for matching of data
encoding with hard systematic error corrections codes
7 2014 T
An Optimized Modified Booth Recoder for Efficient Design of the
Add-Multiply Operator.
8 2014 T Area delay power efficient carry select adder.
9 2014 T Fast radix 10 multipliation using redudant BCD codes.
10 2014 T Recursive Approach to the Design of a Parallel Self-Timed Adder.
11 2014 T Analysis and design of low power double tail comparator.
12 2014 T A Novel Modulo 2N
-2K
-1 Adder for Residue Number System.
13 2014 T Area-Delay Efficient Binary Adders in QCA.
14 2014 T
Low-Complexity Multiplier for GF(2m) Based on All-One
Polynomials.
15 2014 T Smart Reliable Network-on-Chip.
16 2014 J Design of Low Power TPG BIST Technique using LP-LFSR
17 2014 J Design and Implementation of Adder for Modulo 2n
+1 addition
18 2014 J
Implementation and Analysis of High Speed Multipliers – A
Vedic Multipliers Approach.
19 2014 J
Design of High Speed, Area Efficient, Low Power Vedic
Multiplier using Reversible Logic Gate.
20 2014 J
A Low Power Single Phase Clock Distribution Using VLSI
Technology.
21 2014 J
Dynamic Multi Resolution Tracer for on Chip Bus with Real Time
Compression.
22 2014 J
Design and Estimation of delay, power and area for Parallel
prefix adders.
23 2014 J
Design and Implementation of Wishbone Bus Interface
Architecture for SoC Integration USING Verilog

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VLSI M.TECH & B.TECH PROJECT LIST 2015-2016
SL.NO YEAR TITLE
24 2013 T
A Low-Cost, Systematic Methodology for Soft Error Robustness
of Logic Circuits.
25 2013 T Design of Testable Reversible Sequential Circuits.
26 2013 T Multioperand Redundant Adders on FPGAs.
27 2013 T
Reducing the Cost of Implementing Error Correction Codes in
Content Addressable Memories.
28 2013 T
Reducing the Cost of Implementing Error Correction Codes in
Content Addressable Memories.
29 2013 T
The LUT-SR Family of Uniform Random Number Generators for
FPGA Architectures.
30 2013 T
Algorithm and Architecture Design of Bandwidth-Oriented
Motion Estimation for Real-Time Mobile Video Applications.
31 2013 T
Error Detection in Majority Logic Decoding of Euclidean
Geometry Low Density Parity Check (EG-LDPC) Codes.
32 2013 T An Efficient Interpolation-Based Chase BCH Decoder.
33 2013 T
VLSI Implementation of a Low-Cost High-Quality Image Scaling
Processor.
34 2013 T Pipelined Radix- Feedforward FFT Architectures.
35 2013 T
A New VLSI Architecture of Parallel Multiplier–Accumulator
Based on Radix-2 Modified Booth Algorithm.
36 2013 T
Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-
Based SRAM Design.
37 2013 J Design and Simulation of ZIGBEE Transmitter Using Verilog.
38 2013 J
A High Speed Binary Floating Point Multiplier Using Dadda
Algorithm.
39 2013 J
FPGA Implementation of Efficient Hardwarefor the Advanced
Encryption Standard.
40 2013 J
Design and Implementation of 32 Bit Unsigned Multiplier Using
CLAA and CSLA.
41 2013 J VLSI Based Robust Router Architecture
42 2013 J
Fast Search Algorithm Based Anti-collision Technique For RFID
Passive Tag’s.
43 2013 J Design of On-Chip Bus with OCP Interface
44 2013 J
High Speed and Low Power implementation of 3-Weight Pattern
Generation Based on accumulator.
45 2013 J Design & Implementation Of 32-Bit Risc (MIPS) Processor

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VLSI M.TECH & B.TECH PROJECT LIST 2015-2016
SL.NO YEAR TITLE
46 2013 C
VLSI implementation of Fast Addition using Quaternary Signed
Digit Number System.
47 2013 C
High Performance and Power Efficient 32-bit Carry Select Adder
using Hybrid PTL/CMOS Logic Style.
48 2013 C
An FPGA Based High Speed IEEE-754 Double Precision Floating
Point Multiplier Using Verilog.
49
2013 C RTL Design and VLSI Implementation of an efficient
Convolutional Encoder and Adaptive Viterbi Decoder .
50
2013 C VLSI Implementation of a High Speed Single Precision Floating
Point Unit Using Verilog.
51
2013 C Design and implementation of truncated multipliers for precision
improvement.
52 2013 C Design of High Speed and Low Power 15-4 Compressor.
53 2012 T
Design of an Error Detection and Data Recovery Architecture for
Motion Estimation Testing Applications.
54 2012 T An Efficient Architecture for 3-D Discrete Wavelet Transform,
55 2012 T
High-Speed Low-Power Viterbi Decoder Design for TCM
Decoders.
56 2012 T Low-Power and Area-Efficient Carry Select Adder.
57 2012 T
Period Extension and Randomness Enhancement Using High-
Throughput Reseeding-Mixing PRNG.
58 2012 T
An On-Chip AHB Bus Tracer With Real-Time Compression and
Dynamic Multiresolution Supports for SoC.
59 2012 T
An On-Chip Delay Measurement Technique Using Signature
Registers for Small-Delay Defect Detection.
60 2012 T Accumulator Based 3-Weight Pattern Generation.
61 2012 J Implementation of Power Efficient Vedic Multiplier.
62 2012 J
Design and Implementation of OFDM (Orthogonal Frequency
Division Multiplexing) using VHDL and FPGA.
63 2012 J Implementing of an CAN Protocol Using Verilog
64 2012 C
A Novel Approach for Parallel CRC generation for high speed
application.
65 2012 C
A High Speed and Area Efficient Booth Recoded Wallace Tree
Multiplier for fast Arithmetic Circuits.
66 2011 T
Reducing the Computation Time in (Short Bit-Width) Two’s
Complement Multipliers

4. Contact us +91 90148 09480, +91 90359 01870
VLSI M.TECH & B.TECH PROJECT LIST 2015-2016
SL.NO YEAR TITLE
67 2011 T
Self-Immunity Technique to Improve Register File Integrity
against Soft Errors.
68 2011 C
Design and Implementation of Low Power Digital FIR Filter
based on low power multipliers and adders on xilinx FPGA
** T- Transaction
**J- Journal
**C- Conference
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+91 90148 09480
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