2. DESIGN OF MEMS RESONATOR WITH READOUT
May 17, 2015
Micro-electromechanical systems (MEMS) have wide application in the development of sensors for the de-
tection of magnitudes in almost any domain. One particular kind of micromechanical device, which is based
on a silicon cantilever, has been recently developed and used as a very sensitive detector of heat, surface
stress or mass or in molecular recognition. In this project, the cantilever will be driven electrostatically to
the resonance by means of a lateral electrode, which is closely placed parallel to the cantilever. A capaci-
tive read-out of the cantilever oscillation will be performed by means of a CMOS circuitry, which has been
designed to be integrated monolithically with the nanocantilever-driver system. A knowledge as precise as
possible of the electrical characteristics of the cantilever-driver system is crucial for a correct design of the
2 Threshold voltage extraction of a given technology node
2.1 Constant-current method
This methods evaluates the threshold voltage as the value of the gate voltage corresponding to a given
arbitrary constant drain current. Advantages
1. Threshold voltage can be determined quickly with one voltage measurement.
2. Widely used in industry because of its simplicity.
1. Totally dependent on the arbitrary chosen value of drain current.
2.2 Extrapolation in linear region method
This method consist of ﬁnding the gate-voltage axis intercept of the linear extrapolation of the ID − VG at
its maximum ﬁrst derivative(slope) point (i.e. the maximum transconductance, gm) . The value of threshold
voltage is then calculated by adding VD/2 to the resulting gate-voltage axis intercept. Disadvantages
1. Maximum slope might be uncertain.
2. Mobility degradation eﬀect is not taken into consideration.
2.3 Transconductace extrapolation method in linear region
This method suggests that the threshold voltage corresponds to the gate voltage axis intercept of the linear
extrapolation of the gm − VG characteristics at its maximum ﬁrst derivative(slope) point.
3. 2.4 Ratio method
The ratio of drain current to the square root of the transconductance behaves as a linear function of gate
bias, whose intercept with the gate-voltage axis will equal the threshold voltage.
1. Avoid the dependence extracted VT value on mobility degradation and velocity saturation eﬀect.
Considering the dependence of the mobility on the electric ﬁeld, the new expression of the drain current
is presented in equation
1 + θ(VG − VT )
VD(VG − VT ) (1)
The transconductance becomes:
[1 + θ(VG − VT )]2
If the ratio ID/
gm is calculated, it results:
CoxVDµ0(VG − VT ) (3)
It can be seen from the above equation that the ID/
gm ratio is not aﬀected by variations in carrier mobility
due to the transversal electric ﬁeld. It is obvious that the dependence ID/
gm versus VG will be plotted as
a straight line. If the line will be extrapolated at ID = 0 the threshold voltage can be deduced.
Model Parameter used is .MODEL CMOSN NMOS LEVEL=3 PHI=0.600000 TOX=2.1200E-08 XJ=0.200000U +TPG=1
VTO=0.7860 LD=1.6470E-07 KP=9.6379E-05 +UO=591.7 RSH=8.5450E+01 GAMMA=0.5863 +NSUB=2.7470E+16
NFS=1.98E+12 VMAX=1.7330E+05 +CGDO=4.0241E-10 +CGSO=4.0241E-10 +CGBO=3.6144E-10 CJ=3.8541E-04
MJ=1.1854 CJSW=1.3940E-10 +MJSW=0.125195 PB=0.800000
Figure 1: iD vs VG
Vt0 extracted = 0.78 volts
4. Figure 2: gm
Figure 3: iD/
gm vs VG
3 Design of diﬀerential ampliﬁer of a given speciﬁcation
3.1 Design problem speciﬁcation
3.2 Large-signal transconductance characteristics of diﬀerential ampliﬁer
vID = vGS1 − vGS2 =
ISS = iD1 + iD2 (5)
These relationships are useful for vID < 2 ISS/β.
Diﬀerentiating iD1(or iD2) with respect to vID and setting vID = 0 gives transcondutance of diﬀerential
5. Figure 4: Problem speciﬁcation
Figure 5: Transconductor characteristics of diﬀerential ampliﬁer
3.3 Voltage transfer characteristics of diﬀerential ampliﬁer
Voltage transfer characteristics of current mirror load circuit. The diﬀerential-in, diﬀerential-out transcon-
ductance is twice gm and can be written as
3.4 Input common mode range
Another important characteristics of a diﬀerential ampliﬁer is input common mode range,ICMR. ICMR is
found by setting vID to zero and vary vIC until one of the transistor in the diﬀerential ampliﬁer is no longer
6. Figure 6: Voltage transfer characteristics
Highest Common Mode Voltage
vIC(max) = VT N1 + VDD − VSG3 (10)
Lowest Common Mode Voltage
vIC(min) = VSS + VDS5(sat) + VGS2 (11)
3.5 Slew rate
The slew-rate performance of the diﬀerential ampliﬁer depends on the value of ISS and the capacitance from
the output node to ac ground. Slew rate is deﬁned as the maximum output voltage rate, either positive or
negative. Since the slew rate in the diﬀerential ampliﬁer is determined by the amount of current that can
be sourced or sunk into the output capacitor, the slew rate of diﬀerential ampliﬁer is given by
where C is the total capacitance connected to the output node.
3.6 Frequency response of diﬀerential ampliﬁer
3.7 Problem analysis and Spice code
1. Pick ISS to satisfy the slew rate knowing CL and the power dissipation.
2. Check to see if Rout still specify the frequency response, if not change ISS or modify circuit.
3. Design W3/L3(W4/L4) to satisfy the upper ICMR.
4. Design W1/L1(W2/L2) to satisfy gain.
5. Design W5/L5(W6/L6) to satisfy lower ICMR.
1. To meet the slew rate, ISS >= 60µA. For maximum power dissipation, ISS <= 151.15µA
2. f−3db of 100kHz implies that Rout <= 530kΩ . Therefore Rout = 2
(λN +λP )ISS
<= 530kΩ . Choose
ISS = 105.575uA .
8. Vdd 4 0 3.3
mp 2 2 4 4 pmos w=10u l=1u
mp2 3 2 4 4 pmos w=10u l=1u
mn 2 a 1 0 nmos w=120u l=1u
mn1 3 b 1 0 nmos w=120u l=1u
mn2 1 5 0 0 nmos w=4u l=1u
mn3 5 5 0 0 nmos w=4u l=1u
Is 4 5 dc 105.575u
Cl 3 0 3p
vd1 a 7 ac 50mv
vd2 7 b ac 50mv
vcm 7 0 dc 1.55v
.ac dec 10 10 10mega
.plot ac v(3)
3.8 Magnitude plot and Phase plot
Figure 9: Magnitude plot
4 Electromechanical model of a resonating nano-cantilever-based
sensor for high-resolution and high-sensitivity mass detection
4.1 Detection of small changes in mass of the order of attogram
Assume the mass we want to measure is added to the cantilever.
δm = 26k
(fres − δf)2
9. Figure 10: Phase plot
Assume no changes in elastic constant.
4.2 Calculation of snap-in voltage for a given cantilever-driver system
Snap-in voltage is maximum voltage that can be applied if the applied voltage exceeds that value, the
cantilever will colapse into the driver and will remain in that position irreversibly. The snap-in voltage
correspond to the ﬁrst unstable deﬂection of the total potential energy and can be calculated by ﬁnding a
minimum of the ﬁrst derivative of the total potential energy.
xsi = 0.44s (14)
Vsi = 0.22
4.3 Calculation of current through cantilever-driver system at resonance fre-
The static capacitance of the cantilever-driver system, C0, increases when a dc voltage is applied. The new
capacitance Cp is
Cp = C0(1 + κ(Vdc))(F) (16)
where κ is electromechanical coupling parameter calculated by κ = 2k
The model also describes the current component induced by the dc voltage applied to the vibrating
cantilever by a series RSLSCS branch in parallel to Cp :
CS = 1.798κC0 (18)
The total current that ﬂows between the driver and the cantilever is ﬁnally determined by ﬁrstly calculating
the impedance of RSLSCS||Cp and then computing the current induced through this impedance when Vacopt
10. Figure 11: Small signal electromechanical model of oscillating cantilever-driver system.
5 Design of two stage OPAMP
Figure 12: Two stage OPAMP
5.1 Design problem speciﬁcations
1. VDD = 2.5V and VSS=−2.5
2. Av > 5000V/V
3. Gain bandwidth product,GB = 5MHz
4. −1V < ICMR < 2V
5. Slew Rate,SR > 10V/µs
6. CL = 10pF
7. Power Dissipation,PDiss. <= 2mW
11. 8. Phase margin,PM=60◦
5.2 Problem analysis
1. Choose the smallest device length that will keep the channel modulation parameter constant and give
a good matching for current mirror.
2. From the desired phase margin, choose the minimum value for Cc that is, for a 60◦
phase margin choose
Cc < 0.22CL (21)
This assumes z >= 10GB.
3. Determine the minimum value for the ”tail current”’ from
Ibias = SR.Cc (22)
4. Design for S3 from the maximum input voltage speciﬁcation.
kp[VDD − Vin(max) + Vtn + Vtp]2
>= 1 (23)
5. Design for S1(S2) to achieve the desired GB.
gm1 = GB.Cc (24)
6. Design for S5 from the minimum input voltage. First calculate VDS5(sat) then ﬁnd S5.
VDS5 = Vin(min) − VSS −
− Vtn >= 100mV (26)
7. Find the S6 and I6 by letting the second pole(p2) be equal to 2.2 times GB.
gm6 = 10gm1 (28)
S6 = S4
8. Design S7 to achieve the desired current ratio Ibias and I6.
9. Check power dissipation and gain.
PDiss. = (Ibias + I6)(VDD + |VSS|) (32)
Ibias(λ2 + λ3)(λ6 + λ7)
10. If the gain is not met, the current Ibias can be decreased.